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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_sparam.v] - Diff between revs 119 and 131
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/* $Id: aeMB2_sparam.v,v 1.1 2008-04-20 16:33:39 sybreon Exp $
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/* $Id: aeMB2_sparam.v,v 1.2 2008-04-26 01:09:06 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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/**
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/**
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* @file aeMB2_sparam.v
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* @file aeMB2_sparam.v
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* @brief On-chip single-port asynchronous SRAM.
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* @brief On-chip single-port asynchronous SRAM.
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* This will be implemented as distributed RAM.
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* This will be implemented as distributed RAM.
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rRAM[i] <= {(DW){1'b0}};
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rRAM[i] <= {(DW){1'b0}};
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end
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end
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end
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end
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// synopsys translate_on
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// synopsys translate_on
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endmodule // fasm_sparam
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endmodule // aeMB2_sparam
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/*
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Revision 1.1 2008/04/20 16:33:39 sybreon
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Initial import.
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*/
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