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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_tpsram.v] - Diff between revs 131 and 134
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Rev 134 |
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/* $Id: aeMB2_tpsram.v,v 1.2 2008-04-26 01:09:06 sybreon Exp $
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/* $Id: aeMB2_tpsram.v,v 1.3 2008-04-26 17:57:43 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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xdat_o <= {(1+(DW-1)){1'b0}};
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xdat_o <= {(1+(DW-1)){1'b0}};
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// End of automatics
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// End of automatics
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else if (xena_i)
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else if (xena_i)
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xdat_o <= #1 rRAM[xadr_i];
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xdat_o <= #1 rRAM[xadr_i];
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assign dat_o = {(DW){1'bX}};
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assign dat_o = {(DW){1'bX}}; // tieoff unused outputs
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// --- SIMULATION ONLY ------------------------------------
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// --- SIMULATION ONLY ------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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integer i;
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integer i;
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initial begin
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initial begin
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endmodule // aeMB2_tpsram
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endmodule // aeMB2_tpsram
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.2 2008/04/26 01:09:06 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Revision 1.1 2008/04/20 16:33:39 sybreon
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Revision 1.1 2008/04/20 16:33:39 sybreon
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Initial import.
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Initial import.
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*/
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*/
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No newline at end of file
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No newline at end of file
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