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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_xslif.v] - Diff between revs 140 and 147

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Rev 140 Rev 147
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/* $Id: aeMB2_xslif.v,v 1.6 2008-04-27 16:04:12 sybreon Exp $
/* $Id: aeMB2_xslif.v,v 1.7 2008-04-27 16:41:46 sybreon Exp $
**
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
**
** This file is part of AEMB.
** This file is part of AEMB.
Line 95... Line 95...
        xwb_wre_o <= #1 imm_of[15]; // PUT
        xwb_wre_o <= #1 imm_of[15]; // PUT
        xwb_tag_o <= #1 imm_of[13]; // cGET/cPUT        
        xwb_tag_o <= #1 imm_of[13]; // cGET/cPUT        
 
 
        xwb_dat_o <= #1 opa_of; // Latch output
        xwb_dat_o <= #1 opa_of; // Latch output
 
 
        xwb_mx <= #1 (xwb_ack_i) ? xwb_dat_i : xwb_lat; // Latch input
        xwb_mx <= #1 (xwb_ack_i) ?
 
                  xwb_dat_i : // stalled from XWB
 
                  xwb_lat; // Latch earlier
 
 
     end // if (dena)
     end // if (dena)
 
 
   assign xwb_sel_o = 4'hF;
   assign xwb_sel_o = 4'hF;
 
 
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     if (grst) begin
     if (grst) begin
        /*AUTORESET*/
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        // Beginning of autoreset for uninitialized flops
        xwb_lat <= 32'h0;
        xwb_lat <= 32'h0;
        // End of automatics
        // End of automatics
     end else if (xwb_stb_o) begin
     end else if (xwb_ack_i) begin
        xwb_lat <= #1 xwb_dat_i;
        xwb_lat <= #1 xwb_dat_i;
     end
     end
 
 
   always @(posedge gclk)
   always @(posedge gclk)
     if (grst) begin
     if (grst) begin
        /*AUTORESET*/
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        // Beginning of autoreset for uninitialized flops
        xBLK <= 1'h0;
        xBLK <= 1'h0;
        xwb_stb_o <= 1'h0;
        xwb_stb_o <= 1'h0;
        // End of automatics
        // End of automatics
     end else if (dena) begin
     end else if (xwb_fb) begin
        xBLK <= #1 imm_of[14]; // nGET/nPUT     
        xBLK <= #1 imm_of[14]; // nGET/nPUT     
        xwb_stb_o <= #1 (dena) ? !opc_of[5] & opc_of[4] & opc_of[3] & opc_of[1] : // GET/PUT
        xwb_stb_o <= #1 (dena) ? !opc_of[5] & opc_of[4] & opc_of[3] & opc_of[1] : // GET/PUT
                     (xwb_stb_o & !xwb_ack_i);
                     (xwb_stb_o & !xwb_ack_i);
     end
     end
 
 
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endmodule // aeMB2_xslif
endmodule // aeMB2_xslif
 
 
/*
/*
 $Log: not supported by cvs2svn $
 $Log: not supported by cvs2svn $
 
 Revision 1.6  2008/04/27 16:04:12  sybreon
 
 Fixed minor typos.
 
 
 Revision 1.5  2008/04/26 17:57:43  sybreon
 Revision 1.5  2008/04/26 17:57:43  sybreon
 Minor performance improvements.
 Minor performance improvements.
 
 
 Revision 1.4  2008/04/26 01:09:06  sybreon
 Revision 1.4  2008/04/26 01:09:06  sybreon
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.

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