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/*
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/*
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* $Id: aeMB_core.v,v 1.3 2007-04-11 04:30:43 sybreon Exp $
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* $Id: aeMB_core.v,v 1.4 2007-04-25 22:15:04 sybreon Exp $
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*
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*
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* AEMB 32-bit Microblaze Compatible Core
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* AEMB 32-bit Microblaze Compatible Core
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or modify it
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* capable of executing software compile for EDK 2.1 using GCC. It has the
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* capable of executing software compile for EDK 2.1 using GCC. It has the
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* capability of handling interrupts as well as exceptions.
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* capability of handling interrupts as well as exceptions.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.3 2007/04/11 04:30:43 sybreon
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* Added pipeline stalling from incomplete bus cycles.
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* Separated sync and async portions of code.
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*
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* Revision 1.2 2007/04/04 06:13:23 sybreon
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* Revision 1.2 2007/04/04 06:13:23 sybreon
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* Removed unused signals
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* Removed unused signals
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*
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*
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* initial import
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* initial import
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*
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*
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*/
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*/
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module aeMB_core (/*AUTOARG*/
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module aeMB_core (/*AUTOARG*/
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// Outputs
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// Outputs
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iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_dat_o, dwb_adr_o,
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iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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dwb_adr_o,
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// Inputs
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// Inputs
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sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i, iwb_ack_i,
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sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i, iwb_ack_i,
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dwb_dat_i, dwb_ack_i
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dwb_dat_i, dwb_ack_i
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);
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);
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// Instruction WB address space
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// Instruction WB address space
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/*AUTOOUTPUT*/
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v
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output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v
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output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v
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output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v
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output [3:0] dwb_sel_o; // From aslu of aeMB_aslu.v
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output dwb_stb_o; // From decode of aeMB_decode.v
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output dwb_stb_o; // From decode of aeMB_decode.v
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output dwb_we_o; // From decode of aeMB_decode.v
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output dwb_we_o; // From decode of aeMB_decode.v
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output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
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output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
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output iwb_stb_o; // From decode of aeMB_decode.v
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output iwb_stb_o; // From decode of aeMB_decode.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To control of aeMB_control.v
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input dwb_ack_i; // To control of aeMB_control.v
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input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v, ...
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input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v
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input iwb_ack_i; // To control of aeMB_control.v
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input iwb_ack_i; // To control of aeMB_control.v
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input [31:0] iwb_dat_i; // To fetch of aeMB_fetch.v, ...
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input [31:0] iwb_dat_i; // To fetch of aeMB_fetch.v, ...
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input sys_clk_i; // To control of aeMB_control.v
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input sys_clk_i; // To control of aeMB_control.v
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input sys_exc_i; // To control of aeMB_control.v
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input sys_exc_i; // To control of aeMB_control.v
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input sys_int_i; // To control of aeMB_control.v
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input sys_int_i; // To control of aeMB_control.v
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Line 78... |
wire nclk; // From control of aeMB_control.v
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wire nclk; // From control of aeMB_control.v
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wire nrst; // From control of aeMB_control.v
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wire nrst; // From control of aeMB_control.v
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wire nrun; // From control of aeMB_control.v
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wire nrun; // From control of aeMB_control.v
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wire rBRA; // From decode of aeMB_decode.v
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wire rBRA; // From decode of aeMB_decode.v
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wire rDLY; // From decode of aeMB_decode.v
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wire rDLY; // From decode of aeMB_decode.v
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wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v
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wire rDWBSTB; // From decode of aeMB_decode.v
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wire rDWBSTB; // From decode of aeMB_decode.v
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wire rDWBWE; // From decode of aeMB_decode.v
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wire rDWBWE; // From decode of aeMB_decode.v
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wire [1:0] rFSM; // From control of aeMB_control.v
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wire [1:0] rFSM; // From control of aeMB_control.v
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wire [15:0] rIMM; // From decode of aeMB_decode.v
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wire [15:0] rIMM; // From decode of aeMB_decode.v
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wire rIWBSTB; // From decode of aeMB_decode.v
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wire rIWBSTB; // From decode of aeMB_decode.v
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wire [31:0] rREGA; // From regfile of aeMB_regfile.v
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wire [31:0] rREGA; // From regfile of aeMB_regfile.v
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wire [31:0] rREGB; // From regfile of aeMB_regfile.v
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wire [31:0] rREGB; // From regfile of aeMB_regfile.v
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wire [31:0] rRESULT; // From aslu of aeMB_aslu.v
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wire [31:0] rRESULT; // From aslu of aeMB_aslu.v
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wire rRWE; // From decode of aeMB_decode.v
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wire rRWE; // From decode of aeMB_decode.v
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wire [31:0] rSIMM; // From decode of aeMB_decode.v
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wire [31:0] rSIMM; // From decode of aeMB_decode.v
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wire [31:0] sDWBDAT; // From regfile of aeMB_regfile.v
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// End of automatics
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// End of automatics
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aeMB_regfile #(DSIZ)
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aeMB_regfile #(DSIZ)
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regfile (/*AUTOINST*/
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regfile (/*AUTOINST*/
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// Outputs
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// Outputs
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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.rREGB (rREGB[31:0]),
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.rREGB (rREGB[31:0]),
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.sDWBDAT (sDWBDAT[31:0]),
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// Inputs
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// Inputs
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.dwb_dat_i (dwb_dat_i[31:0]),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.rDWBSTB (rDWBSTB),
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.rDWBSTB (rDWBSTB),
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.rDWBWE (rDWBWE),
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.rDWBWE (rDWBWE),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRD_ (rRD_[4:0]),
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.rRD_ (rRD_[4:0]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rFSM (rFSM[1:0]),
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.rFSM (rFSM[1:0]),
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.rPC (rPC[31:0]),
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.rPC (rPC[31:0]),
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.rOPC (rOPC[5:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rLNK (rLNK),
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.rLNK (rLNK),
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.rRWE (rRWE),
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.rRWE (rRWE),
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.nclk (nclk),
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.nclk (nclk),
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.nrst (nrst),
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.nrst (nrst),
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.drun (drun),
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.drun (drun),
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Line 169... |
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aeMB_aslu #(DSIZ)
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aeMB_aslu #(DSIZ)
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aslu (/*AUTOINST*/
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aslu (/*AUTOINST*/
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// Outputs
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// Outputs
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.dwb_adr_o (dwb_adr_o[DSIZ-1:0]),
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.dwb_adr_o (dwb_adr_o[DSIZ-1:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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// Inputs
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// Inputs
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.dwb_dat_i (dwb_dat_i[31:0]),
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.sDWBDAT (sDWBDAT[31:0]),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.rDLY (rDLY),
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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.rREGB (rREGB[31:0]),
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.rREGB (rREGB[31:0]),
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.rSIMM (rSIMM[31:0]),
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.rSIMM (rSIMM[31:0]),
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Line 218... |
.rMXLDST (rMXLDST[1:0]),
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.rMXLDST (rMXLDST[1:0]),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_we_o (dwb_we_o),
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.dwb_we_o (dwb_we_o),
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// Inputs
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// Inputs
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.sDWBDAT (sDWBDAT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.nclk (nclk),
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.nclk (nclk),
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.nrst (nrst),
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.nrst (nrst),
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.drun (drun),
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.drun (drun),
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.frun (frun),
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.frun (frun),
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.nrun (nrun));
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.nrun (nrun));
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