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/*
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// $Id: aeMB_core.v,v 1.9 2007-11-23 14:06:41 sybreon Exp $
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* $Id: aeMB_core.v,v 1.8 2007-10-22 19:12:59 sybreon Exp $
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//
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*
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// AEMB 32'bit RISC MICROPROCESSOR CORE
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* AEMB 32-bit Microblaze Compatible Core
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//
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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//
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* This library is free software; you can redistribute it and/or
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// This file is part of AEMB.
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* modify it under the terms of the GNU Lesser General Public License
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//
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* as published by the Free Software Foundation; either version 2.1 of
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// AEMB is free software: you can redistribute it and/or modify it
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* the License, or (at your option) any later version.
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// under the terms of the GNU Lesser General Public License as
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*
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// published by the Free Software Foundation, either version 3 of the
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* This library is distributed in the hope that it will be useful, but
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// License, or (at your option) any later version.
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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//
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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* Lesser General Public License for more details.
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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*
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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* You should have received a copy of the GNU Lesser General Public
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// Public License for more details.
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* License along with this library; if not, write to the Free Software
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//
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// You should have received a copy of the GNU Lesser General Public
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* USA
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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*
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//
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* DESCRIPTION
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// HISTORY
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* Microblaze compatible, WISHBONE compliant hardware core. This core is
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// $Log: not supported by cvs2svn $
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* capable of executing software compile for EDK 2.1 using GCC. It has the
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// Revision 1.8 2007/10/22 19:12:59 sybreon
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* capability of handling interrupts as well as exceptions.
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// Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.
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*
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//
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* HISTORY
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// Revision 1.7 2007/05/30 18:44:30 sybreon
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* $Log: not supported by cvs2svn $
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// Added interrupt support.
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* Revision 1.7 2007/05/30 18:44:30 sybreon
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//
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* Added interrupt support.
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// Revision 1.6 2007/05/17 09:08:21 sybreon
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*
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// Removed asynchronous reset signal.
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* Revision 1.6 2007/05/17 09:08:21 sybreon
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//
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* Removed asynchronous reset signal.
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// Revision 1.5 2007/04/27 00:23:55 sybreon
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*
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// Added code documentation.
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* Revision 1.5 2007/04/27 00:23:55 sybreon
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// Improved size & speed of rtl/verilog/aeMB_aslu.v
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* Added code documentation.
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//
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* Improved size & speed of rtl/verilog/aeMB_aslu.v
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// Revision 1.4 2007/04/25 22:15:04 sybreon
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*
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// Added support for 8-bit and 16-bit data types.
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* Revision 1.4 2007/04/25 22:15:04 sybreon
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//
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* Added support for 8-bit and 16-bit data types.
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// Revision 1.3 2007/04/11 04:30:43 sybreon
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*
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// Added pipeline stalling from incomplete bus cycles.
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* Revision 1.3 2007/04/11 04:30:43 sybreon
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// Separated sync and async portions of code.
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* Added pipeline stalling from incomplete bus cycles.
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//
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* Separated sync and async portions of code.
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// Revision 1.2 2007/04/04 06:13:23 sybreon
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*
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// Removed unused signals
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* Revision 1.2 2007/04/04 06:13:23 sybreon
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//
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* Removed unused signals
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// Revision 1.1 2007/03/09 17:52:17 sybreon
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*
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// initial import
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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//
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* initial import
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*
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*/
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module aeMB_core (/*AUTOARG*/
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module aeMB_core (/*AUTOARG*/
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// Outputs
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// Outputs
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iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
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dwb_adr_o,
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fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
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// Inputs
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// Inputs
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
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dwb_ack_i
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fsl_ack_i, dwb_dat_i, dwb_ack_i
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);
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);
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// Instruction WB address space
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// Instruction WB address space
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parameter ISIZ = 32;
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parameter ISIZ = 32;
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// Data WB address space
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// Data WB address space
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parameter DSIZ = 32;
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parameter DSIZ = 32;
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// Multiplier
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parameter MUL = 1;
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// Barrel Shifter
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parameter BSF = 1;
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/*AUTOOUTPUT*/
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v
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output [DSIZ-1:2] dwb_adr_o; // From edk32 of aeMB_edk32.v
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output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v
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output [31:0] dwb_dat_o; // From edk32 of aeMB_edk32.v
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output [3:0] dwb_sel_o; // From aslu of aeMB_aslu.v
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output [3:0] dwb_sel_o; // From edk32 of aeMB_edk32.v
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output dwb_stb_o; // From decode of aeMB_decode.v
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output dwb_stb_o; // From edk32 of aeMB_edk32.v
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output dwb_we_o; // From decode of aeMB_decode.v
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output dwb_wre_o; // From edk32 of aeMB_edk32.v
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output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
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output [6:2] fsl_adr_o; // From edk32 of aeMB_edk32.v
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output iwb_stb_o; // From fetch of aeMB_fetch.v
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output [31:0] fsl_dat_o; // From edk32 of aeMB_edk32.v
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output fsl_stb_o; // From edk32 of aeMB_edk32.v
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output [1:0] fsl_tag_o; // From edk32 of aeMB_edk32.v
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output fsl_wre_o; // From edk32 of aeMB_edk32.v
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output [ISIZ-1:2] iwb_adr_o; // From edk32 of aeMB_edk32.v
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output iwb_stb_o; // From edk32 of aeMB_edk32.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To control of aeMB_control.v
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input dwb_ack_i; // To edk32 of aeMB_edk32.v
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input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v
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input [31:0] dwb_dat_i; // To edk32 of aeMB_edk32.v
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input iwb_ack_i; // To control of aeMB_control.v
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input fsl_ack_i; // To edk32 of aeMB_edk32.v
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input [31:0] iwb_dat_i; // To fetch of aeMB_fetch.v, ...
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input [31:0] fsl_dat_i; // To edk32 of aeMB_edk32.v
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input sys_clk_i; // To control of aeMB_control.v
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input iwb_ack_i; // To edk32 of aeMB_edk32.v
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input sys_int_i; // To control of aeMB_control.v
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input [31:0] iwb_dat_i; // To edk32 of aeMB_edk32.v
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input sys_rst_i; // To control of aeMB_control.v
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input sys_clk_i; // To edk32 of aeMB_edk32.v
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input sys_int_i; // To edk32 of aeMB_edk32.v
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input sys_rst_i; // To edk32 of aeMB_edk32.v
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// End of automatics
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// End of automatics
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire drun; // From control of aeMB_control.v
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wire frun; // From control of aeMB_control.v
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wire nclk; // From control of aeMB_control.v
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wire prst; // From control of aeMB_control.v
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wire prun; // From control of aeMB_control.v
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wire [1:0] rATOM; // From decode of aeMB_decode.v
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wire rBRA; // From decode of aeMB_decode.v
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wire rDLY; // From decode of aeMB_decode.v
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wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v
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wire rDWBSTB; // From decode of aeMB_decode.v
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wire rDWBWE; // From decode of aeMB_decode.v
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wire [2:0] rFSM; // From control of aeMB_control.v
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wire [15:0] rIMM; // From decode of aeMB_decode.v
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wire rIWBSTB; // From fetch of aeMB_fetch.v
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wire rLNK; // From decode of aeMB_decode.v
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wire rMSR_IE; // From aslu of aeMB_aslu.v
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wire [1:0] rMXALU; // From decode of aeMB_decode.v
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wire [1:0] rMXLDST; // From decode of aeMB_decode.v
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wire [1:0] rMXSRC; // From decode of aeMB_decode.v
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wire [1:0] rMXTGT; // From decode of aeMB_decode.v
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wire [5:0] rOPC; // From decode of aeMB_decode.v
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wire [31:0] rPC; // From fetch of aeMB_fetch.v
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wire [4:0] rRA; // From decode of aeMB_decode.v
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wire [4:0] rRB; // From decode of aeMB_decode.v
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wire [4:0] rRD; // From decode of aeMB_decode.v
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wire [31:0] rREGA; // From regfile of aeMB_regfile.v
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wire [31:0] rREGB; // From regfile of aeMB_regfile.v
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wire [31:0] rRESULT; // From aslu of aeMB_aslu.v
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wire rRWE; // From decode of aeMB_decode.v
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wire [31:0] rSIMM; // From decode of aeMB_decode.v
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wire [31:0] sDWBDAT; // From regfile of aeMB_regfile.v
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// End of automatics
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// INSTANTIATIONS /////////////////////////////////////////////////////////////////
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// INSTANTIATIONS /////////////////////////////////////////////////////////////////
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aeMB_regfile #(DSIZ)
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/*
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regfile (/*AUTOINST*/
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aeMB_edk32 AUTO_TEMPLATE (
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// Outputs
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.dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
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.rREGA (rREGA[31:0]),
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);
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.rREGB (rREGB[31:0]),
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*/
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.sDWBDAT (sDWBDAT[31:0]),
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// Inputs
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.dwb_dat_i (dwb_dat_i[31:0]),
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.rDWBSTB (rDWBSTB),
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.rDWBWE (rDWBWE),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rRD (rRD[4:0]),
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.rRESULT (rRESULT[31:0]),
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.rFSM (rFSM[2:0]),
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.rPC (rPC[31:0]),
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.rOPC (rOPC[5:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rLNK (rLNK),
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.rRWE (rRWE),
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.nclk (nclk),
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.prst (prst),
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.drun (drun),
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.prun (prun));
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aeMB_fetch #(ISIZ)
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aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF)
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fetch (/*AUTOINST*/
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edk32 (/*AUTOINST*/
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// Outputs
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// Outputs
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.iwb_adr_o (iwb_adr_o[ISIZ-1:0]),
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.dwb_adr_o (dwb_adr_o[DSIZ-1:2]), // Templated
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.dwb_stb_o (dwb_stb_o),
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.dwb_wre_o (dwb_wre_o),
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.fsl_adr_o (fsl_adr_o[6:2]),
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.fsl_dat_o (fsl_dat_o[31:0]),
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.fsl_stb_o (fsl_stb_o),
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.fsl_tag_o (fsl_tag_o[1:0]),
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.fsl_wre_o (fsl_wre_o),
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.iwb_adr_o (iwb_adr_o[ISIZ-1:2]), // Templated
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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.rPC (rPC[31:0]),
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.rIWBSTB (rIWBSTB),
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// Inputs
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// Inputs
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.dwb_ack_i (dwb_ack_i),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.fsl_ack_i (fsl_ack_i),
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.fsl_dat_i (fsl_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.nclk (nclk),
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.prst (prst),
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.prun (prun),
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.rFSM (rFSM[2:0]),
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.rBRA (rBRA),
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.rRESULT (rRESULT[31:0]));
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aeMB_control
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control (/*AUTOINST*/
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// Outputs
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.rFSM (rFSM[2:0]),
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.nclk (nclk),
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.prst (prst),
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.prun (prun),
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.frun (frun),
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.drun (drun),
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// Inputs
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.sys_rst_i (sys_rst_i),
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.sys_clk_i (sys_clk_i),
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.sys_int_i (sys_int_i),
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.sys_int_i (sys_int_i),
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.rIWBSTB (rIWBSTB),
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.sys_clk_i (sys_clk_i),
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.iwb_ack_i (iwb_ack_i),
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.sys_rst_i (sys_rst_i));
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.rDWBSTB (rDWBSTB),
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.dwb_ack_i (dwb_ack_i),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.rMSR_IE (rMSR_IE),
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.rATOM (rATOM[1:0]));
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aeMB_aslu #(DSIZ)
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aslu (/*AUTOINST*/
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// Outputs
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.dwb_adr_o (dwb_adr_o[DSIZ-1:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rMSR_IE (rMSR_IE),
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// Inputs
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.sDWBDAT (sDWBDAT[31:0]),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.rREGA (rREGA[31:0]),
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.rREGB (rREGB[31:0]),
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.rSIMM (rSIMM[31:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXALU (rMXALU[1:0]),
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.rOPC (rOPC[5:0]),
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.rPC (rPC[31:0]),
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.rIMM (rIMM[15:0]),
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.rRD (rRD[4:0]),
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.rRA (rRA[4:0]),
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.rMXLDST (rMXLDST[1:0]),
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.rFSM (rFSM[2:0]),
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.nclk (nclk),
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.prst (prst),
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.drun (drun),
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.prun (prun));
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aeMB_decode
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decode (/*AUTOINST*/
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// Outputs
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.rSIMM (rSIMM[31:0]),
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.rMXALU (rMXALU[1:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rRD (rRD[4:0]),
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.rOPC (rOPC[5:0]),
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.rIMM (rIMM[15:0]),
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.rDWBSTB (rDWBSTB),
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.rDWBWE (rDWBWE),
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.rDLY (rDLY),
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.rLNK (rLNK),
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.rBRA (rBRA),
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.rRWE (rRWE),
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.rMXLDST (rMXLDST[1:0]),
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.rATOM (rATOM[1:0]),
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.dwb_stb_o (dwb_stb_o),
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.dwb_we_o (dwb_we_o),
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// Inputs
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.sDWBDAT (sDWBDAT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rREGA (rREGA[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rFSM (rFSM[2:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.nclk (nclk),
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.prst (prst),
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.drun (drun),
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.frun (frun),
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.prun (prun));
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endmodule // aeMB_core
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endmodule // aeMB_core
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No newline at end of file
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No newline at end of file
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