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// $Id: aeMB_ctrl.v,v 1.1 2007-11-02 03:25:40 sybreon Exp $
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// $Id: aeMB_ctrl.v,v 1.2 2007-11-02 19:20:58 sybreon Exp $
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//
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//
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// AEMB CONTROL UNIT
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// AEMB CONTROL UNIT
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2007/11/02 03:25:40 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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module aeMB_ctrl (/*AUTOARG*/
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module aeMB_ctrl (/*AUTOARG*/
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// Outputs
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// Outputs
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rXCE,
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, dwb_stb_o,
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dwb_stb_o, dwb_wre_o,
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dwb_wre_o,
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// Inputs
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// Inputs
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rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, gclk,
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rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
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grst, gena, sys_int_i
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gclk, grst, gena
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);
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);
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// INTERNAL
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// INTERNAL
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//output [31:2] rPCLNK;
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//output [31:2] rPCLNK;
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output [1:0] rMXDST;
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output [1:0] rMXDST;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [2:0] rMXALU;
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output [2:0] rMXALU;
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output [4:0] rRW;
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output [4:0] rRW;
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output rDWBSTB;
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output rDWBSTB;
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output [1:0] rXCE;
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input [1:0] rXCE;
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input rDLY;
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input rDLY;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [10:0] rALT;
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input [10:0] rALT;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [4:0] rRD, rRA, rRB;
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input [4:0] rRD, rRA, rRB;
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output dwb_stb_o;
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output dwb_stb_o;
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output dwb_wre_o;
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output dwb_wre_o;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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input sys_int_i;
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// --- DECODE INSTRUCTIONS
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// --- DECODE INSTRUCTIONS
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// TODO: Simplify
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// TODO: Simplify
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wire fSFT = (rOPC == 6'o44);
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wire fSFT = (rOPC == 6'o44);
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reg [31:2] rPCLNK, xPCLNK;
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reg [31:2] rPCLNK, xPCLNK;
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reg [1:0] rMXDST, xMXDST;
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reg [1:0] rMXDST, xMXDST;
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reg [4:0] rRW, xRW;
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reg [4:0] rRW, xRW;
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wire fSKIP = rBRA & !rDLY;
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wire fSKIP = (rBRA & !rDLY);
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR)
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or rXCE)
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if (fSKIP) begin
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if (fSKIP | |rXCE) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xDWBSTB <= 1'h0;
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xDWBSTB <= 1'h0;
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xDWBWRE <= 1'h0;
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xDWBWRE <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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xDWBSTB <= fLOD | fSTR;
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xDWBSTB <= fLOD | fSTR;
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xDWBWRE <= fSTR;
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xDWBWRE <= fSTR;
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end
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end
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always @(/*AUTOSENSE*/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR
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always @(/*AUTOSENSE*/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR
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or rRD)
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or rRD or rXCE)
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if (fSKIP) begin
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if (fSKIP) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xMXDST <= 2'h0;
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xMXDST <= 2'h0;
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xRW <= 5'h0;
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xRW <= 5'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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case (rXCE)
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//xPCLNK <= rPC;
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2'o2: xMXDST <= 2'o1;
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default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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/*
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case (rXCE)
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2'o1: xMXDST <= 2'o1;
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default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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(fLOD) ? 2'o2 :
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(fBRU) ? 2'o1 :
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2'o0;
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endcase // case (rXCE)
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case (rXCE)
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2'o1: xRW <= 5'd14;
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default: xRW <= rRD;
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endcase // case (rXCE)
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*/
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xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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(fLOD) ? 2'o2 :
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(fLOD) ? 2'o2 :
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(fBRU) ? 2'o1 :
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(fBRU) ? 2'o1 :
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2'o0;
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2'o0;
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endcase
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xRW <= rRD;
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end
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// --- INTERRUPT CONTROL ---------------------------------
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wire fNCLR;
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assign fNCLR = (rOPC == 6'o46) | (rOPC == 6'o56) | // BRU
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(rOPC == 6'o47) | (rOPC == 6'o57) | // BCC
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(rOPC == 6'o55) | // RTD
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(rOPC == 6'o54); // IMM
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reg [2:0] rINT;
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reg [1:0] rXCE, xXCE;
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//wire fINT = rINT[0] & rINT[1] & !rINT[2] & rMSR_IE; // +Edge
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wire fINT = rINT[2] & rMSR_IE;
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always @(/*AUTOSENSE*/fINT or fNCLR or rXCE)
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case (rXCE)
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case (rXCE)
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2'o0: xXCE <= (fINT & !fNCLR) ? 2'o1 : 2'o0;
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2'o2: xRW <= 5'd14;
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default: xXCE <= 2'o0;
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default: xRW <= rRD;
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endcase // case (rXCE)
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endcase
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end // else: !if(fSKIP)
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rINT <= 3'h0;
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// End of automatics
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end else if (gena) begin
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rINT <= #1 {rINT[1:0], sys_int_i & rMSR_IE};
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end
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// --- PIPELINE CONTROL DELAY ----------------------------
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// --- PIPELINE CONTROL DELAY ----------------------------
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBSTB <= 1'h0;
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rDWBSTB <= 1'h0;
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rDWBWRE <= 1'h0;
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rDWBWRE <= 1'h0;
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rMXDST <= 2'h0;
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rMXDST <= 2'h0;
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rRW <= 5'h0;
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rRW <= 5'h0;
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rXCE <= 2'h0;
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// End of automatics
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// End of automatics
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end else if (gena) begin
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end else if (gena) begin
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//rPCLNK <= #1 xPCLNK;
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//rPCLNK <= #1 xPCLNK;
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rMXDST <= #1 xMXDST;
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rMXDST <= #1 xMXDST;
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rRW <= #1 xRW;
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rRW <= #1 xRW;
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rDWBSTB <= #1 xDWBSTB;
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rDWBSTB <= #1 xDWBSTB;
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rDWBWRE <= #1 xDWBWRE;
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rDWBWRE <= #1 xDWBWRE;
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rXCE <= #1 xXCE;
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end
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end
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endmodule // aeMB_ctrl
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endmodule // aeMB_ctrl
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