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// $Id: aeMB_ctrl.v,v 1.9 2007-11-15 09:26:43 sybreon Exp $
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// $Id: aeMB_ctrl.v,v 1.10 2007-11-30 16:44:40 sybreon Exp $
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//
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//
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// AEMB CONTROL UNIT
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// AEMB CONTROL UNIT
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2007/11/15 09:26:43 sybreon
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// Fixed minor typo causing synthesis failure.
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//
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// Revision 1.8 2007/11/14 23:19:24 sybreon
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// Revision 1.8 2007/11/14 23:19:24 sybreon
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// Fixed minor typo.
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// Fixed minor typo.
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//
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//
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// Revision 1.7 2007/11/14 22:14:34 sybreon
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// Revision 1.7 2007/11/14 22:14:34 sybreon
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// Changed interrupt handling system (reported by M. Ettus).
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// Changed interrupt handling system (reported by M. Ettus).
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//output [31:2] rPCLNK;
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//output [31:2] rPCLNK;
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output [1:0] rMXDST;
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output [1:0] rMXDST;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [2:0] rMXALU;
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output [2:0] rMXALU;
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output [4:0] rRW;
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output [4:0] rRW;
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//output rDWBSTB;
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//output rFSLSTB;
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//input [1:0] rXCE;
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input rDLY;
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input rDLY;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [10:0] rALT;
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input [10:0] rALT;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [4:0] rRD, rRA, rRB;
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input [4:0] rRD, rRA, rRB;
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reg [1:0] rMXALT, xMXALT;
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reg [1:0] rMXALT, xMXALT;
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// --- OPERAND SELECTOR ---------------------------------
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// --- OPERAND SELECTOR ---------------------------------
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/*
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wire fRDWE = |rRW;
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wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
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wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
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wire fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;
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wire fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;
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assign rMXSRC = (fBRU | fBCC) ? 2'o3 : // PC
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(fAFWD_M) ? 2'o2: // RAM
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(fAFWD_R) ? 2'o1: // FWD
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2'o0; // REG
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assign rMXTGT = (rOPC[3]) ? 2'o3 : // IMM
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(fBFWD_M) ? 2'o2 : // RAM
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(fBFWD_R) ? 2'o1 : // FWD
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2'o0; // REG
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assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM
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(fAFWD_R) ? 2'o1 : // FWD
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2'o0; // REG
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*/
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wire wRDWE = |xRW;
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wire wRDWE = |xRW;
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wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
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wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
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wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
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wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
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wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
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wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
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wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
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wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
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(wBFWD_R) ? 2'o1 : // FWD
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(wBFWD_R) ? 2'o1 : // FWD
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2'o0; // REG
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2'o0; // REG
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xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
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xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
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(wAFWD_R) ? 2'o1 : // FWD
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(wAFWD_R) ? 2'o1 : // FWD
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2'o0; // REG
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2'o0; // REG
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end
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end // else: !if(rBRA)
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// --- ALU CONTROL ---------------------------------------
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// --- ALU CONTROL ---------------------------------------
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/*
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reg [2:0] rMXALU;
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always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
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or fSFT) begin
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rMXALU <= (fBRA | fMOV) ? 3'o3 :
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(fSFT) ? 3'o2 :
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(fLOG) ? 3'o1 :
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(fMUL) ? 3'o4 :
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(fBSF) ? 3'o5 :
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(fDIV) ? 3'o6 :
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3'o0;
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end
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*/
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reg [2:0] rMXALU, xMXALU;
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reg [2:0] rMXALU, xMXALU;
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always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
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always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
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or wMUL or wSFT)
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or wMUL or wSFT)
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//if (rBRA | |rXCE) begin
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//if (rBRA | |rXCE) begin
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(wLOG) ? 3'o1 :
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(wLOG) ? 3'o1 :
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(wMUL) ? 3'o4 :
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(wMUL) ? 3'o4 :
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(wBSF) ? 3'o5 :
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(wBSF) ? 3'o5 :
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(wDIV) ? 3'o6 :
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(wDIV) ? 3'o6 :
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3'o0;
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3'o0;
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end
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end // else: !if(rBRA)
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// --- DELAY SLOT REGISTERS ------------------------------
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// --- DELAY SLOT REGISTERS ------------------------------
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wire fSKIP = (rBRA & !rDLY);
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wire fSKIP = (rBRA & !rDLY);
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xMXDST <= 2'h0;
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xMXDST <= 2'h0;
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xRW <= 5'h0;
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xRW <= 5'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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/*
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case (rXCE)
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2'o2: xMXDST <= 2'o1;
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default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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(fLOD | fGET) ? 2'o2 :
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(fBRU) ? 2'o1 :
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2'o0;
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endcase
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case (rXCE)
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2'o2: xRW <= 5'd14;
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default: xRW <= rRD;
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endcase
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*/
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xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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(fLOD | fGET) ? 2'o2 :
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(fLOD | fGET) ? 2'o2 :
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(fBRU) ? 2'o1 :
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(fBRU) ? 2'o1 :
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2'o0;
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2'o0;
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xRW <= rRD;
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xRW <= rRD;
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rMXDST <= 2'h0;
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rMXDST <= 2'h0;
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rMXSRC <= 2'h0;
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rMXSRC <= 2'h0;
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rMXTGT <= 2'h0;
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rMXTGT <= 2'h0;
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rRW <= 5'h0;
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rRW <= 5'h0;
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// End of automatics
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// End of automatics
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end else if (gena) begin
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end else if (gena) begin // if (grst)
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//rPCLNK <= #1 xPCLNK;
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//rPCLNK <= #1 xPCLNK;
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rMXDST <= #1 xMXDST;
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rMXDST <= #1 xMXDST;
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rRW <= #1 xRW;
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rRW <= #1 xRW;
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rMXSRC <= #1 xMXSRC;
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rMXSRC <= #1 xMXSRC;
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rMXTGT <= #1 xMXTGT;
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rMXTGT <= #1 xMXTGT;
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