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/* $Id: aeMB_edk32.v,v 1.12 2007-12-23 20:40:44 sybreon Exp $
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/* $Id: aeMB_edk32.v,v 1.13 2007-12-25 22:15:09 sybreon Exp $
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**
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**
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** AEMB EDK 3.2 Compatible Core
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** AEMB EDK 3.2 Compatible Core
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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wire [31:0] rREGA; // From regf of aeMB_regf.v
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wire [31:0] rREGA; // From regf of aeMB_regf.v
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wire [31:0] rREGB; // From regf of aeMB_regf.v
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wire [31:0] rREGB; // From regf of aeMB_regf.v
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wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
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wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
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wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
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wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
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wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
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wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
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wire rSTALL; // From ibuf of aeMB_ibuf.v
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wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v
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wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v
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// End of automatics
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// End of automatics
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input sys_clk_i;
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input sys_clk_i;
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input sys_rst_i;
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input sys_rst_i;
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wire grst = sys_rst_i;
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wire grst = sys_rst_i;
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wire gclk = sys_clk_i;
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wire gclk = sys_clk_i;
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wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
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wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL;
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// --- INSTANTIATIONS -------------------------------------
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// --- INSTANTIATIONS -------------------------------------
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aeMB_ibuf
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aeMB_ibuf
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ibuf (/*AUTOINST*/
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ibuf (/*AUTOINST*/
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rALT (rALT[10:0]),
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.rALT (rALT[10:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rSIMM (rSIMM[31:0]),
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.rSIMM (rSIMM[31:0]),
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.xIREG (xIREG[31:0]),
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.xIREG (xIREG[31:0]),
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.rSTALL (rSTALL),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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// Inputs
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// Inputs
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rMSR_IE (rMSR_IE),
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.rMSR_IE (rMSR_IE),
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.rMSR_BIP (rMSR_BIP),
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.rMSR_BIP (rMSR_BIP),
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rMXALU (rMXALU[2:0]),
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.rMXALU (rMXALU[2:0]),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.rDLY (rDLY),
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.rALT (rALT[10:0]),
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.rALT (rALT[10:0]),
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.rSTALL (rSTALL),
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.rSIMM (rSIMM[31:0]),
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.rSIMM (rSIMM[31:0]),
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.rIMM (rIMM[15:0]),
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.rIMM (rIMM[15:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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endmodule // aeMB_edk32
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endmodule // aeMB_edk32
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.12 2007/12/23 20:40:44 sybreon
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Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
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Revision 1.11 2007/11/30 17:08:29 sybreon
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Revision 1.11 2007/11/30 17:08:29 sybreon
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Moved simulation kernel into code.
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Moved simulation kernel into code.
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Revision 1.10 2007/11/16 21:52:03 sybreon
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Revision 1.10 2007/11/16 21:52:03 sybreon
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Added fsl_tag_o to FSL bus (tag either address or data).
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Added fsl_tag_o to FSL bus (tag either address or data).
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