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/* $Id: aeMB_ibuf.v,v 1.8 2007-12-25 22:15:09 sybreon Exp $
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/* $Id: aeMB_ibuf.v,v 1.9 2008-01-19 16:01:22 sybreon Exp $
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**
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**
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** AEMB INSTRUCTION BUFFER
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** AEMB INSTRUCTION BUFFER
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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module aeMB_ibuf (/*AUTOARG*/
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module aeMB_ibuf (/*AUTOARG*/
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// Outputs
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// Outputs
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rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
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rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
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// Inputs
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// Inputs
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rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
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rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
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grst, gena
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grst, gena, oena
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);
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);
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// INTERNAL
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// INTERNAL
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output [15:0] rIMM;
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output [15:0] rIMM;
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output [4:0] rRA, rRD, rRB;
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output [4:0] rRA, rRD, rRB;
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output [10:0] rALT;
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output [10:0] rALT;
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// SYSTEM
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// SYSTEM
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input sys_int_i;
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input sys_int_i;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena, oena;
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reg [15:0] rIMM;
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reg [15:0] rIMM;
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reg [4:0] rRA, rRD;
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reg [4:0] rRA, rRD;
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reg [5:0] rOPC;
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reg [5:0] rOPC;
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rSTALL <= 1'h0;
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rSTALL <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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rSTALL <= #1 !rSTALL & (fMUL | fBSF);
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rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL);
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end
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end
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endmodule // aeMB_ibuf
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endmodule // aeMB_ibuf
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.8 2007/12/25 22:15:09 sybreon
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Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
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Revision 1.7 2007/11/22 15:11:15 sybreon
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Revision 1.7 2007/11/22 15:11:15 sybreon
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Change interrupt to positive level triggered interrupts.
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Change interrupt to positive level triggered interrupts.
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Revision 1.6 2007/11/14 23:39:51 sybreon
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Revision 1.6 2007/11/14 23:39:51 sybreon
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Fixed interrupt signal synchronisation.
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Fixed interrupt signal synchronisation.
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