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// $Id: aeMB_ibuf.v,v 1.1 2007-11-02 03:25:40 sybreon Exp $
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// $Id: aeMB_ibuf.v,v 1.2 2007-11-02 19:20:58 sybreon Exp $
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//
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//
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// AEMB INSTRUCTION BUFFER
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// AEMB INSTRUCTION BUFFER
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2007/11/02 03:25:40 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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module aeMB_ibuf (/*AUTOARG*/
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module aeMB_ibuf (/*AUTOARG*/
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// Outputs
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// Outputs
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rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, iwb_stb_o,
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rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, iwb_stb_o,
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// Inputs
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// Inputs
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// TODO: Assign to FIFO not full.
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// TODO: Assign to FIFO not full.
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assign iwb_stb_o = 1'b1;
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assign iwb_stb_o = 1'b1;
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reg [31:0] rSIMM, xSIMM;
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reg [31:0] rSIMM, xSIMM;
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wire [31:0] wSIMM = (fIMM) ? {rIMM, wIDAT[15:0]} : { {(16){wIDAT[15]}}, wIDAT[15:0]}; // TODO: Factor
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wire fIMM = (rOPC == 6'o54);
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wire fIMM = (rOPC == 6'o54);
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reg [31:0] xIREG;
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reg [31:0] xIREG;
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// DELAY SLOT
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// DELAY SLOT
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always @(/*AUTOSENSE*/rBRA or wIDAT)
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always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or rXCE or wIDAT) begin
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if (rBRA) begin
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xIREG <= (rBRA | |rXCE) ? 32'h88000000 : wIDAT;
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xIREG <= 32'h88000000;
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xSIMM <= (fIMM) ? {rIMM, wIDAT[15:0]} : { {(16){wIDAT[15]}}, wIDAT[15:0]};
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/*AUTORESET*/
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end else begin
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xIREG <= wIDAT; // FIXME: Simplify
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//xSIMM <= wSIMM;
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end
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always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or xIREG)
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if (rBRA) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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xSIMM <= 32'h0;
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// End of automatics
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end else begin
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//xIREG <= wIDAT; // FIXME: Simplify
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xSIMM <= (fIMM) ? {rIMM, xIREG[15:0]} : { {(16){xIREG[15]}}, xIREG[15:0]}; // TODO: Factor
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end
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end
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// Synchronous
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// Synchronous
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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