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/* $Id: aeMB_xecu.v,v 1.10 2007-12-25 22:15:09 sybreon Exp $
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/* $Id: aeMB_xecu.v,v 1.11 2008-01-19 15:57:36 sybreon Exp $
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**
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**
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** AEMB MAIN EXECUTION ALU
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** AEMB MAIN EXECUTION ALU
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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// --- MSR REGISTER -----------------
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// --- MSR REGISTER -----------------
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// C
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// C
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wire fMTS = (rOPC == 6'o45) & rIMM[14];
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wire fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP;
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
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always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
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or rOPA or rRES_ADDC or rRES_SFTC)
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or rOPA or rRES_ADDC or rRES_SFTC)
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//if (fSKIP | |rXCE) begin
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//if (fSKIP | |rXCE) begin
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3'o2: xMSR_C <= rRES_SFTC; // SHIFT
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3'o2: xMSR_C <= rRES_SFTC; // SHIFT
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3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
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3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
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3'o4: xMSR_C <= rMSR_C;
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3'o4: xMSR_C <= rMSR_C;
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3'o5: xMSR_C <= rMSR_C;
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3'o5: xMSR_C <= rMSR_C;
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default: xMSR_C <= 1'hX;
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default: xMSR_C <= 1'hX;
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endcase
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endcase // case (rMXALU)
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// IE/BIP/BE
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// IE/BIP/BE
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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wire fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP;
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wire fRTBD = (rOPC == 6'o55) & rRD[1];
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wire fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP;
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
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wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
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wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
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always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA)
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always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA)
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xMSR_IE <= (fINT) ? 1'b0 :
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xMSR_IE <= (fINT) ? 1'b0 :
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rMSR_BIP <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_C <= 1'h0;
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rMSR_C <= 1'h0;
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rMSR_IE <= 1'h0;
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rMSR_IE <= 1'h0;
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rRESULT <= 32'h0;
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rRESULT <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (gena) begin
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end else if (gena) begin // if (grst)
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rRESULT <= #1 xRESULT;
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rRESULT <= #1 xRESULT;
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rDWBSEL <= #1 xDWBSEL;
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rDWBSEL <= #1 xDWBSEL;
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rMSR_C <= #1 xMSR_C;
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rMSR_C <= #1 xMSR_C;
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rMSR_IE <= #1 xMSR_IE;
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rMSR_IE <= #1 xMSR_IE;
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rMSR_BE <= #1 xMSR_BE;
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rMSR_BE <= #1 xMSR_BE;
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endmodule // aeMB_xecu
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endmodule // aeMB_xecu
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.10 2007/12/25 22:15:09 sybreon
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Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
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Revision 1.9 2007/11/30 16:42:51 sybreon
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Revision 1.9 2007/11/30 16:42:51 sybreon
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Minor code cleanup.
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Minor code cleanup.
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Revision 1.8 2007/11/16 21:52:03 sybreon
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Revision 1.8 2007/11/16 21:52:03 sybreon
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Added fsl_tag_o to FSL bus (tag either address or data).
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Added fsl_tag_o to FSL bus (tag either address or data).
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