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// $Id: aeMB_xecu.v,v 1.3 2007-11-03 08:34:55 sybreon Exp $
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// $Id: aeMB_xecu.v,v 1.4 2007-11-08 14:17:47 sybreon Exp $
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//
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//
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// AEMB MAIN EXECUTION ALU
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// AEMB MAIN EXECUTION ALU
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2007/11/03 08:34:55 sybreon
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// Minor code cleanup.
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//
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Added better (beta) interrupt support.
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// Added better (beta) interrupt support.
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// Changed MSR_IE to disabled at reset as per MB docs.
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// Changed MSR_IE to disabled at reset as per MB docs.
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//
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//
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// Revision 1.1 2007/11/02 03:25:41 sybreon
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// Revision 1.1 2007/11/02 03:25:41 sybreon
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module aeMB_xecu (/*AUTOARG*/
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module aeMB_xecu (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, rRESULT, rOPA, rOPB, rDWBSEL, rMSR_IE,
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dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL, rMSR_IE, rMSR_BIP,
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rMSR_BIP,
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// Inputs
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// Inputs
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rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rMXALU, rBRA, rDLY, rSIMM,
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rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rMXALU, rBRA, rDLY, rALT,
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rIMM, rOPC, rRD, rDWBDI, rPC, rRES_MUL, rRES_BSF, gclk, grst, gena
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rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
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);
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);
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parameter DW=32;
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parameter DW=32;
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parameter MUL=0;
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parameter BSF=0;
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// DATA WISHBONE
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// DATA WISHBONE
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output [DW-1:2] dwb_adr_o;
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output [DW-1:2] dwb_adr_o;
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output [3:0] dwb_sel_o;
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output [3:0] dwb_sel_o;
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// INTERNAL
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// INTERNAL
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output [31:0] rRESULT;
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output [31:0] rRESULT;
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output [31:0] rOPA, rOPB;
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output [3:0] rDWBSEL;
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output [3:0] rDWBSEL;
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output rMSR_IE;
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output rMSR_IE;
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output rMSR_BIP;
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output rMSR_BIP;
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input [1:0] rXCE;
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input [1:0] rXCE;
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input [31:0] rREGA, rREGB;
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input [31:0] rREGA, rREGB;
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input [1:0] rMXSRC, rMXTGT;
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input [1:0] rMXSRC, rMXTGT;
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input [4:0] rRA;
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input [4:0] rRA;
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input [2:0] rMXALU;
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input [2:0] rMXALU;
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input rBRA, rDLY;
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input rBRA, rDLY;
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input [10:0] rALT;
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//input [1:0] rXCE;
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input [31:0] rSIMM;
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input [31:0] rSIMM;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [4:0] rRD;
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input [4:0] rRD;
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input [31:0] rDWBDI;
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input [31:0] rDWBDI;
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input [31:2] rPC;
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input [31:2] rPC;
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input [31:0] rRES_MUL; // External Multiplier
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//input [31:0] rRES_MUL; // External Multiplier
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input [31:0] rRES_BSF; // External Barrel Shifter
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//input [31:0] rRES_BSF; // External Barrel Shifter
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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reg rMSR_C, xMSR_C;
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reg rMSR_C, xMSR_C;
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2'o2: rOPB <= rDWBDI;
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2'o2: rOPB <= rDWBDI;
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2'o3: rOPB <= rSIMM;
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2'o3: rOPB <= rSIMM;
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endcase // case (rMXTGT)
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endcase // case (rMXTGT)
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// --- ADD/SUB SELECTOR ----
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// --- ADD/SUB SELECTOR ----
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// FIXME: Redesign
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// TODO: Refactor
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// TODO: Refactor
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// TODO: Verify signed compare
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// TODO: Verify signed compare
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wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
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wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
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wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;
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wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;
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4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
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4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
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4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
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4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
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default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
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default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
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endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
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endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
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// --- LOGIC SELECTOR ---
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// --- LOGIC SELECTOR --------------------------------------
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reg [31:0] rRES_LOG;
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reg [31:0] rRES_LOG;
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always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
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always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
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case (rOPC[1:0])
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case (rOPC[1:0])
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2'o0: rRES_LOG <= #1 rOPA | rOPB;
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2'o0: rRES_LOG <= #1 rOPA | rOPB;
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2'o1: rRES_LOG <= #1 rOPA & rOPB;
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2'o1: rRES_LOG <= #1 rOPA & rOPB;
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2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
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2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
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2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
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2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
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endcase // case (rOPC[1:0])
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endcase // case (rOPC[1:0])
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// --- SHIFT SELECTOR ---
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// --- SHIFTER SELECTOR ------------------------------------
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reg [31:0] rRES_SFT;
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reg [31:0] rRES_SFT;
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reg rRES_SFTC;
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reg rRES_SFTC;
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always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
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always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
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2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]};
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2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]};
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2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} :
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2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} :
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{ {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
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{ {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
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endcase // case (rIMM[6:5])
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endcase // case (rIMM[6:5])
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// --- MOVE SELECTOR ---
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// --- MOVE SELECTOR ---------------------------------------
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wire [31:0] wMSR = {rMSR_C, 3'o0,
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wire [31:0] wMSR = {rMSR_C, 3'o0,
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20'h0ED32,
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20'h0ED32,
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4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE};
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4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE};
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wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
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wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
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rRES_MOV <= (fMFSR) ? wMSR :
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rRES_MOV <= (fMFSR) ? wMSR :
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(fMFPC) ? rPC :
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(fMFPC) ? rPC :
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(rRA[3]) ? rOPB :
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(rRA[3]) ? rOPB :
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rOPA;
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rOPA;
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// --- MULTIPLIER ------------------------------------------
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reg [31:0] rRES_MUL;
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always @(/*AUTOSENSE*/rOPA or rOPB) begin
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rRES_MUL <= (rOPA * rOPB);
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end
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// --- BARREL SHIFTER --------------------------------------
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reg [31:0] rRES_BSF;
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reg [31:0] xBSRL, xBSRA, xBSLL;
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// Infer a logical left barrel shifter.
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always @(/*AUTOSENSE*/rOPA or rOPB)
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xBSLL <= rOPA << rOPB[4:0];
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// Infer a logical right barrel shifter.
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always @(/*AUTOSENSE*/rOPA or rOPB)
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xBSRL <= rOPA >> rOPB[4:0];
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// Infer a arithmetic right barrel shifter.
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always @(/*AUTOSENSE*/rOPA or rOPB)
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case (rOPB[4:0])
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5'd00: xBSRA <= rOPA;
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5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
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5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
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5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};
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5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};
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5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};
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5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};
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5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};
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5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};
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5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};
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5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};
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5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};
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5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};
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5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};
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5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};
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5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};
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5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};
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5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};
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5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};
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5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};
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5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};
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5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};
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5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};
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5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};
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5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};
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5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};
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5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};
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5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};
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5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};
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5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
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5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
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5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
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endcase // case (rOPB[4:0])
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always @(/*AUTOSENSE*/rALT or xBSLL or xBSRA or xBSRL)
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case (rALT[10:9])
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2'd0: rRES_BSF <= xBSRL;
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2'd1: rRES_BSF <= xBSRA;
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2'd2: rRES_BSF <= xBSLL;
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default: rRES_BSF <= 32'hX;
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endcase // case (rALT[10:9])
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// --- MSR REGISTER -----------------
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// --- MSR REGISTER -----------------
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// C
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// C
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wire fMTS = (rOPC == 6'o45) & rIMM[14];
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wire fMTS = (rOPC == 6'o45) & rIMM[14];
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Line 274... |
rMSR_BIP;
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rMSR_BIP;
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always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA)
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always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA)
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xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE;
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xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE;
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// --- RESULT SELECTOR
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// --- RESULT SELECTOR -------------------------------------------
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// Selects results from functional units.
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reg [31:0] rRESULT, xRESULT;
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reg [31:0] rRESULT, xRESULT;
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// RESULT
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// RESULT
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always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF
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always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF
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or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT)
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or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT)
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case (rMXALU)
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case (rMXALU)
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3'o0: xRESULT <= rRES_ADD;
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3'o0: xRESULT <= rRES_ADD;
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3'o1: xRESULT <= rRES_LOG;
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3'o1: xRESULT <= rRES_LOG;
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3'o2: xRESULT <= rRES_SFT;
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3'o2: xRESULT <= rRES_SFT;
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3'o3: xRESULT <= rRES_MOV;
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3'o3: xRESULT <= rRES_MOV;
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3'o4: xRESULT <= rRES_MUL;
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3'o4: xRESULT <= (MUL) ? rRES_MUL : 32'hX;
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3'o5: xRESULT <= rRES_BSF;
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3'o5: xRESULT <= (BSF) ? rRES_BSF : 32'hX;
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default: xRESULT <= 32'hX;
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default: xRESULT <= 32'hX;
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endcase // case (rMXALU)
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endcase // case (rMXALU)
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// --- DATA WISHBONE -----
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// --- DATA WISHBONE -----
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