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// $Id: aeMB_xecu.v,v 1.4 2007-11-08 14:17:47 sybreon Exp $
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// $Id: aeMB_xecu.v,v 1.5 2007-11-09 20:51:52 sybreon Exp $
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//
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//
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// AEMB MAIN EXECUTION ALU
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// AEMB MAIN EXECUTION ALU
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2007/11/08 14:17:47 sybreon
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// Parameterised optional components.
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//
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// Revision 1.3 2007/11/03 08:34:55 sybreon
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// Revision 1.3 2007/11/03 08:34:55 sybreon
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// Minor code cleanup.
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// Minor code cleanup.
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//
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//
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Added better (beta) interrupt support.
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// Added better (beta) interrupt support.
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module aeMB_xecu (/*AUTOARG*/
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module aeMB_xecu (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL, rMSR_IE, rMSR_BIP,
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dwb_adr_o, dwb_sel_o, fsl_adr_o, rRESULT, rDWBSEL, rMSR_IE,
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rMSR_BIP,
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// Inputs
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// Inputs
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rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rMXALU, rBRA, rDLY, rALT,
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rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY,
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rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
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rALT, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
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);
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);
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parameter DW=32;
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parameter DW=32;
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parameter MUL=0;
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parameter MUL=0;
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parameter BSF=0;
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parameter BSF=0;
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// DATA WISHBONE
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// DATA WISHBONE
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output [DW-1:2] dwb_adr_o;
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output [DW-1:2] dwb_adr_o;
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output [3:0] dwb_sel_o;
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output [3:0] dwb_sel_o;
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// FSL WISHBONE
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output [14:2] fsl_adr_o;
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// INTERNAL
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// INTERNAL
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output [31:0] rRESULT;
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output [31:0] rRESULT;
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output [3:0] rDWBSEL;
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output [3:0] rDWBSEL;
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output rMSR_IE;
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output rMSR_IE;
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output rMSR_BIP;
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output rMSR_BIP;
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input [1:0] rXCE;
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input [1:0] rXCE;
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input [31:0] rREGA, rREGB;
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input [31:0] rREGA, rREGB;
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input [1:0] rMXSRC, rMXTGT;
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input [1:0] rMXSRC, rMXTGT;
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input [4:0] rRA;
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input [4:0] rRA, rRB;
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input [2:0] rMXALU;
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input [2:0] rMXALU;
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input rBRA, rDLY;
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input rBRA, rDLY;
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input [10:0] rALT;
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input [10:0] rALT;
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input [31:0] rSIMM;
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input [31:0] rSIMM;
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assign dwb_adr_o = rRESULT[DW-1:2];
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assign dwb_adr_o = rRESULT[DW-1:2];
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assign dwb_sel_o = rDWBSEL;
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assign dwb_sel_o = rDWBSEL;
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always @(/*AUTOSENSE*/rOPC or wADD)
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always @(/*AUTOSENSE*/rOPC or wADD)
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case (rOPC[1:0])
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case (rOPC[1:0])
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2'o0: case (wADD[1:0])
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2'o0: case (wADD[1:0]) // 8'bit
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2'o0: xDWBSEL <= 4'h8;
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2'o0: xDWBSEL <= 4'h8;
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2'o1: xDWBSEL <= 4'h4;
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2'o1: xDWBSEL <= 4'h4;
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2'o2: xDWBSEL <= 4'h2;
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2'o2: xDWBSEL <= 4'h2;
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2'o3: xDWBSEL <= 4'h1;
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2'o3: xDWBSEL <= 4'h1;
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endcase // case (wADD[1:0])
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endcase // case (wADD[1:0])
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2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC;
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2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit
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2'o2: xDWBSEL <= 4'hF;
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2'o2: xDWBSEL <= 4'hF; // 32'bit
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default: xDWBSEL <= 4'hX;
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2'o3: xDWBSEL <= 4'h0; // FSL
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endcase // case (rOPC[1:0])
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endcase // case (rOPC[1:0])
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// --- FSL WISHBONE --------------------
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reg [14:2] rFSLADR, xFSLADR;
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assign fsl_adr_o = rFSLADR[14:2];
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always @(/*AUTOSENSE*/rALT or rRB) begin
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xFSLADR <= {rALT, rRB[3:2]};
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end
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// --- SYNC ---
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// --- SYNC ---
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBSEL <= 4'h0;
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rDWBSEL <= 4'h0;
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rFSLADR <= 13'h0;
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rMSR_BE <= 1'h0;
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rMSR_BE <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_C <= 1'h0;
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rMSR_C <= 1'h0;
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rMSR_IE <= 1'h0;
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rMSR_IE <= 1'h0;
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rRESULT <= 32'h0;
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rRESULT <= 32'h0;
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rDWBSEL <= #1 xDWBSEL;
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rDWBSEL <= #1 xDWBSEL;
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rMSR_C <= #1 xMSR_C;
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rMSR_C <= #1 xMSR_C;
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rMSR_IE <= #1 xMSR_IE;
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rMSR_IE <= #1 xMSR_IE;
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rMSR_BE <= #1 xMSR_BE;
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rMSR_BE <= #1 xMSR_BE;
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rMSR_BIP <= #1 xMSR_BIP;
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rMSR_BIP <= #1 xMSR_BIP;
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rFSLADR <= #1 xFSLADR;
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end
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end
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endmodule // aeMB_xecu
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endmodule // aeMB_xecu
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