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// $Id: aeMB_xecu.v,v 1.6 2007-11-10 16:39:38 sybreon Exp $
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// $Id: aeMB_xecu.v,v 1.7 2007-11-14 22:14:34 sybreon Exp $
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//
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//
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// AEMB MAIN EXECUTION ALU
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// AEMB MAIN EXECUTION ALU
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2007/11/10 16:39:38 sybreon
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// Upgraded license to LGPLv3.
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// Significant performance optimisations.
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//
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// Revision 1.5 2007/11/09 20:51:52 sybreon
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// Revision 1.5 2007/11/09 20:51:52 sybreon
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// Added GET/PUT support through a FSL bus.
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// Added GET/PUT support through a FSL bus.
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//
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//
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// Revision 1.4 2007/11/08 14:17:47 sybreon
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// Revision 1.4 2007/11/08 14:17:47 sybreon
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// Parameterised optional components.
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// Parameterised optional components.
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module aeMB_xecu (/*AUTOARG*/
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module aeMB_xecu (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, fsl_adr_o, rRESULT, rDWBSEL, rMSR_IE,
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dwb_adr_o, dwb_sel_o, fsl_adr_o, rRESULT, rDWBSEL, rMSR_IE,
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rMSR_BIP,
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rMSR_BIP,
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// Inputs
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// Inputs
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rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY,
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rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT,
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rALT, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
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rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
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);
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);
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parameter DW=32;
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parameter DW=32;
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parameter MUL=0;
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parameter MUL=0;
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parameter BSF=0;
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parameter BSF=0;
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// INTERNAL
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// INTERNAL
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output [31:0] rRESULT;
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output [31:0] rRESULT;
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output [3:0] rDWBSEL;
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output [3:0] rDWBSEL;
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output rMSR_IE;
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output rMSR_IE;
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output rMSR_BIP;
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output rMSR_BIP;
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input [1:0] rXCE;
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//input [1:0] rXCE;
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input [31:0] rREGA, rREGB;
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input [31:0] rREGA, rREGB;
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input [1:0] rMXSRC, rMXTGT;
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input [1:0] rMXSRC, rMXTGT;
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input [4:0] rRA, rRB;
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input [4:0] rRA, rRB;
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input [2:0] rMXALU;
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input [2:0] rMXALU;
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input rBRA, rDLY;
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input rBRA, rDLY;
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// C
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// C
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wire fMTS = (rOPC == 6'o45) & rIMM[14];
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wire fMTS = (rOPC == 6'o45) & rIMM[14];
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
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always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
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or rOPA or rRES_ADDC or rRES_SFTC or rXCE)
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or rOPA or rRES_ADDC or rRES_SFTC)
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if (fSKIP | |rXCE) begin
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//if (fSKIP | |rXCE) begin
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if (fSKIP) begin
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xMSR_C <= rMSR_C;
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xMSR_C <= rMSR_C;
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end else
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end else
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case (rMXALU)
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case (rMXALU)
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
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3'o1: xMSR_C <= rMSR_C; // LOGIC
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3'o1: xMSR_C <= rMSR_C; // LOGIC
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endcase
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endcase
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// IE/BIP/BE
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// IE/BIP/BE
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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wire fRTID = (rOPC == 6'o55) & rRD[0];
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wire fRTBD = (rOPC == 6'o55) & rRD[1];
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wire fRTBD = (rOPC == 6'o55) & rRD[1];
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA[4:2] == 3'o3);
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
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wire fXCE = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
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always @(/*AUTOSENSE*/fMTS or fRTID or rMSR_IE or rOPA or rXCE)
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always @(/*AUTOSENSE*/fMTS or fRTID or fXCE or rMSR_IE or rOPA)
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xMSR_IE <= (rXCE == 2'o2) ? 1'b0 :
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xMSR_IE <= (fXCE) ? 1'b0 :
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(fRTID) ? 1'b1 :
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(fRTID) ? 1'b1 :
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(fMTS) ? rOPA[1] :
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(fMTS) ? rOPA[1] :
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rMSR_IE;
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rMSR_IE;
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always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA)
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always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA)
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