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[/] [aemb/] [trunk/] [sim/] [verilog/] [edk32.v] - Diff between revs 95 and 163

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/* $Id: edk32.v,v 1.12 2007-12-23 20:40:51 sybreon Exp $
/* $Id: edk32.v,v 1.13 2008-05-30 14:02:49 sybreon Exp $
**
**
** AEMB EDK 3.2 Compatible Core TEST
** AEMB EDK 3.2 Compatible Core TEST
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
**
** This file is part of AEMB.
** This file is part of AEMB.
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**
**
** You should have received a copy of the GNU Lesser General Public
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
*/
 
 
`define AEMB_SIMULATION_KERNEL
`include "random.v"
 
 
module edk32 ();
module edk32 ();
 
 
`include "random.v"
 
 
 
   // INITIAL SETUP //////////////////////////////////////////////////////
   // INITIAL SETUP //////////////////////////////////////////////////////
 
 
   reg       sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
   reg       sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
   reg       svc;
   reg       svc;
   integer   inttime;
   integer   inttime;
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   integer   theend;
   integer   theend;
 
 
   always #5 sys_clk_i = ~sys_clk_i;
   always #5 sys_clk_i = ~sys_clk_i;
 
 
   initial begin
   initial begin
      //$dumpfile("dump.vcd");
      `ifdef VCD_DUMP
      //$dumpvars(1,dut);
      $dumpfile("dump.vcd");
   end
      $dumpvars(1,dut);
 
      `endif
 
 
   initial begin
      //seed = `randseed;
      seed = randseed;
 
      theend = 0;
      theend = 0;
      svc = 0;
      svc = 0;
      sys_clk_i = $random(seed);
      sys_clk_i = $random(`randseed);
      sys_rst_i = 1;
      sys_rst_i = 1;
      sys_int_i = 0;
      sys_int_i = 0;
      sys_exc_i = 0;
      sys_exc_i = 0;
      #50 sys_rst_i = 0;
      #50 sys_rst_i = 0;
   end
      #40000000 $displayh("\n*** TIMEOUT ",$stime," ***"); $finish;
 
 
   initial fork
 
      //inttime $display("FSADFASDFSDAF");      
 
      //#10000 sys_int_i = 1;
 
      //#1100 sys_int_i = 0;
 
      //#100000 $displayh("\nTest Completed."); 
 
      //#4000 $finish;
 
   join
 
 
 
 
   end
 
 
   // FAKE MEMORY ////////////////////////////////////////////////////////
   // FAKE MEMORY ////////////////////////////////////////////////////////
 
 
   wire        fsl_stb_o;
   wire        fsl_stb_o;
   wire        fsl_wre_o;
   wire        fsl_wre_o;
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endmodule // edk32
endmodule // edk32
 
 
/*
/*
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 Revision 1.12  2007/12/23 20:40:51  sybreon
 
 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
 
 
 Revision 1.11  2007/12/11 00:44:31  sybreon
 Revision 1.11  2007/12/11 00:44:31  sybreon
 Modified for AEMB2
 Modified for AEMB2
 
 
 Revision 1.10  2007/11/30 17:08:30  sybreon
 Revision 1.10  2007/11/30 17:08:30  sybreon
 Moved simulation kernel into code.
 Moved simulation kernel into code.

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