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// $Id: edk32.v,v 1.3 2007-11-05 10:59:31 sybreon Exp $
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// $Id: edk32.v,v 1.4 2007-11-08 14:18:00 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core TEST
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// AEMB EDK 3.2 Compatible Core TEST
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2007/11/05 10:59:31 sybreon
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// Added random seed for simulation.
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//
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// Revision 1.2 2007/11/02 19:16:10 sybreon
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// Revision 1.2 2007/11/02 19:16:10 sybreon
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// Added interrupt simulation.
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// Added interrupt simulation.
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// Changed "human readable" simulation output.
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// Changed "human readable" simulation output.
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//
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//
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// Revision 1.1 2007/11/02 03:25:45 sybreon
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// Revision 1.1 2007/11/02 03:25:45 sybreon
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integer seed;
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integer seed;
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always #5 sys_clk_i = ~sys_clk_i;
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always #5 sys_clk_i = ~sys_clk_i;
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initial begin
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initial begin
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//$dumpfile("dump.vcd");
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$dumpfile("dump.vcd");
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//$dumpvars(1,dut);
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$dumpvars(1,dut);
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end
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end
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initial begin
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initial begin
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seed = randseed;
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seed = randseed;
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svc = 0;
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svc = 0;
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// ALU
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// ALU
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$write("\t");
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$write("\t");
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//$writeh(" I=",dut.rSIMM);
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//$writeh(" I=",dut.rSIMM);
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$writeh(" A=",dut.rOPA);
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$writeh(" A=",dut.xecu.rOPA);
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$writeh(" B=",dut.rOPB);
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$writeh(" B=",dut.xecu.rOPB);
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case (dut.rMXALU)
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case (dut.rMXALU)
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3'o0: $write(" ADD");
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3'o0: $write(" ADD");
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3'o1: $write(" LOG");
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3'o1: $write(" LOG");
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3'o2: $write(" SFT");
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3'o2: $write(" SFT");
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