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// $Id: edk32.v,v 1.6 2007-11-13 23:37:28 sybreon Exp $
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// $Id: edk32.v,v 1.7 2007-11-14 22:11:41 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core TEST
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// AEMB EDK 3.2 Compatible Core TEST
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// This library is free software; you can redistribute it and/or
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// This file is part of AEMB.
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// modify it under the terms of the GNU Lesser General Public License
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//
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// as published by the Free Software Foundation; either version 2.1 of
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// AEMB is free software: you can redistribute it and/or modify it
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// the License, or (at your option) any later version.
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// under the terms of the GNU Lesser General Public License as
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//
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// published by the Free Software Foundation, either version 3 of the
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// This library is distributed in the hope that it will be useful, but
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// License, or (at your option) any later version.
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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//
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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// Lesser General Public License for more details.
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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// Public License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2007/11/13 23:37:28 sybreon
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// Updated simulation to also check BRI 0x00 instruction.
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//
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// Revision 1.5 2007/11/09 20:51:53 sybreon
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// Revision 1.5 2007/11/09 20:51:53 sybreon
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// Added GET/PUT support through a FSL bus.
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// Added GET/PUT support through a FSL bus.
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//
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//
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// Revision 1.4 2007/11/08 14:18:00 sybreon
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// Revision 1.4 2007/11/08 14:18:00 sybreon
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// Parameterised optional components.
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// Parameterised optional components.
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always #5 sys_clk_i = ~sys_clk_i;
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always #5 sys_clk_i = ~sys_clk_i;
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initial begin
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initial begin
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//$dumpfile("dump.vcd");
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//$dumpfile("dump.vcd");
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//$dumpvars(1,dut);
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//$dumpvars(1,dut);
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//$dumpvars(1,dut.scon);
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end
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end
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initial begin
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initial begin
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seed = randseed;
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seed = randseed;
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theend = 0;
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theend = 0;
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svc = 0;
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svc = 0;
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sys_clk_i = $random(seed);
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sys_clk_i = $random(seed);
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sys_rst_i = 1;
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sys_rst_i = 1;
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sys_int_i = 0;
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sys_int_i = 0;
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sys_exc_i = 0;
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sys_exc_i = 0;
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#30 sys_rst_i = 0;
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#50 sys_rst_i = 0;
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end
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end
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initial fork
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initial fork
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//inttime $display("FSADFASDFSDAF");
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//inttime $display("FSADFASDFSDAF");
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//#10000 sys_int_i = 1;
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//#10000 sys_int_i = 1;
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wire [3:0] dwb_sel_o;
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wire [3:0] dwb_sel_o;
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wire [31:0] dwb_dat_o;
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wire [31:0] dwb_dat_o;
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wire [15:2] dwb_adr_o;
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wire [15:2] dwb_adr_o;
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wire [31:0] dwb_dat_t;
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wire [31:0] dwb_dat_t;
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initial begin
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dwb_ack_i = 0;
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iwb_ack_i = 0;
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fsl_ack_i = 0;
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end
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assign {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
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assign {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
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assign {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
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assign {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
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assign {dwb_dat_t} = ram[dwb_adr_o];
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assign {dwb_dat_t} = ram[dwb_adr_o];
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assign fsl_dat_i = fsl_adr_o;
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assign fsl_dat_i = fsl_adr_o;
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always @(negedge sys_clk_i) begin
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//`define POSEDGE
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`ifdef POSEDGE
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always @(posedge sys_clk_i)
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if (sys_rst_i) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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dwb_ack_i <= 1'h0;
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fsl_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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// End of automatics
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end else begin
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iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
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dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
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fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
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end
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always @(posedge sys_clk_i) begin
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iadr <= #1 iwb_adr_o;
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dadr <= #1 dwb_adr_o;
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if (dwb_we_o & dwb_stb_o) begin
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case (dwb_sel_o)
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4'h1: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_t[7:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_t[31:8],dwb_dat_o[31:24]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_t[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_o[31:24]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]};
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endcase // case (dwb_sel_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // always @ (negedge sys_clk_i)
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`else // !`ifdef POSEDGE
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always @(negedge sys_clk_i)
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if (sys_rst_i) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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dwb_ack_i <= 1'h0;
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fsl_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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// End of automatics
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end else begin
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iwb_ack_i <= #1 iwb_stb_o;
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iwb_ack_i <= #1 iwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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fsl_ack_i <= #1 fsl_stb_o;
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fsl_ack_i <= #1 fsl_stb_o;
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end
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always @(negedge sys_clk_i) begin
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= dwb_adr_o;
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dadr <= #1 dwb_adr_o;
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if (dwb_we_o & dwb_stb_o) begin
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if (dwb_we_o & dwb_stb_o) begin
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
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4'h1: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]};
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // always @ (negedge sys_clk_i)
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end // always @ (negedge sys_clk_i)
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`endif // !`ifdef POSEDGE
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integer i;
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integer i;
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initial begin
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initial begin
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for (i=0;i<65535;i=i+1) begin
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for (i=0;i<65535;i=i+1) begin
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ram[i] <= $random;
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ram[i] <= $random;
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end
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end
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if (($stime > inttime + 500) && !svc) begin
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if (($stime > inttime + 500) && !svc) begin
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$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
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$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
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$finish;
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$finish;
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end
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end
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if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
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if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
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if (|dut.rXCE) svc = 1;
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if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
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svc = 1;
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//$display("\nLATENCY: ", ($stime - inttime)/10);
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end
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// Pass/Fail Monitors
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// Pass/Fail Monitors
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if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
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if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
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$display("\n\tFAIL");
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$display("\n\tFAIL");
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$finish;
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$finish;
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$write ("\n", ($stime/10));
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$write ("\n", ($stime/10));
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$writeh ("\tPC=", {iwb_adr_o,2'd0});
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$writeh ("\tPC=", {iwb_adr_o,2'd0});
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// DECODE
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// DECODE
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$writeh ("\t");
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$writeh ("\t");
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/*
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case (dut.bpcu.rATOM)
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case (dut.bpcu.rATOM)
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2'o2, 2'o1: $write("/");
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2'o2, 2'o1: $write("/");
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2'o0, 2'o3: $write("\\");
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2'o0, 2'o3: $write("\\");
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endcase // case (dut.bpcu.rATOM)
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endcase // case (dut.bpcu.rATOM)
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*/
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case ({dut.rBRA, dut.rDLY})
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case ({dut.rBRA, dut.rDLY})
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2'b00: $write(" ");
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2'b00: $write(" ");
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2'b01: $write(".");
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2'b01: $write(".");
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2'b10: $write("-");
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2'b10: $write("-");
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