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[/] [aemb/] [trunk/] [sim/] [verilog/] [edk32.v] - Diff between revs 59 and 67

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// $Id: edk32.v,v 1.7 2007-11-14 22:11:41 sybreon Exp $
// $Id: edk32.v,v 1.8 2007-11-18 19:41:45 sybreon Exp $
//
//
// AEMB EDK 3.2 Compatible Core TEST
// AEMB EDK 3.2 Compatible Core TEST
//
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
//  
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//
//
// You should have received a copy of the GNU Lesser General Public
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.7  2007/11/14 22:11:41  sybreon
 
// Added posedge/negedge bus interface.
 
// Modified interrupt test system.
 
//
// Revision 1.6  2007/11/13 23:37:28  sybreon
// Revision 1.6  2007/11/13 23:37:28  sybreon
// Updated simulation to also check BRI 0x00 instruction.
// Updated simulation to also check BRI 0x00 instruction.
//
//
// Revision 1.5  2007/11/09 20:51:53  sybreon
// Revision 1.5  2007/11/09 20:51:53  sybreon
// Added GET/PUT support through a FSL bus.
// Added GET/PUT support through a FSL bus.
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   integer   theend;
   integer   theend;
 
 
   always #5 sys_clk_i = ~sys_clk_i;
   always #5 sys_clk_i = ~sys_clk_i;
 
 
   initial begin
   initial begin
      //$dumpfile("dump.vcd");
      $dumpfile("dump.vcd");
      //$dumpvars(1,dut);
      $dumpvars(1,dut);
      //$dumpvars(1,dut.scon);      
      //$dumpvars(1,dut.scon);      
   end
   end
 
 
   initial begin
   initial begin
      seed = randseed;
      seed = randseed;
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   join
   join
 
 
 
 
   // FAKE MEMORY ////////////////////////////////////////////////////////
   // FAKE MEMORY ////////////////////////////////////////////////////////
 
 
   wire [14:2] fsl_adr_o;
 
   wire        fsl_stb_o;
   wire        fsl_stb_o;
   wire        fsl_wre_o;
   wire        fsl_wre_o;
   wire [31:0] fsl_dat_o;
   wire [31:0] fsl_dat_o;
   wire [31:0] fsl_dat_i;
   wire [31:0] fsl_dat_i;
 
   wire [6:2]  fsl_adr_o;
 
 
   wire [15:2] iwb_adr_o;
   wire [15:2] iwb_adr_o;
   wire        iwb_stb_o;
   wire        iwb_stb_o;
   wire        dwb_stb_o;
   wire        dwb_stb_o;
   reg [31:0]  rom [0:65535];
   reg [31:0]  rom [0:65535];

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