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// $Id: edk32.v,v 1.11 2007-12-11 00:44:31 sybreon Exp $
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/* $Id: edk32.v,v 1.12 2007-12-23 20:40:51 sybreon Exp $
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//
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**
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// AEMB EDK 3.2 Compatible Core TEST
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** AEMB EDK 3.2 Compatible Core TEST
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//
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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//
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** This file is part of AEMB.
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// This file is part of AEMB.
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**
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//
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** AEMB is free software: you can redistribute it and/or modify it
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// AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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// under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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// published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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// License, or (at your option) any later version.
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**
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//
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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// Public License for more details.
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**
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//
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** You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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*/
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2007/11/30 17:08:30 sybreon
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// Moved simulation kernel into code.
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//
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// Revision 1.9 2007/11/20 18:36:00 sybreon
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// Removed unnecessary byte acrobatics with VMEM data.
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//
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// Revision 1.8 2007/11/18 19:41:45 sybreon
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// Minor simulation fixes.
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//
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// Revision 1.7 2007/11/14 22:11:41 sybreon
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// Added posedge/negedge bus interface.
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// Modified interrupt test system.
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//
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// Revision 1.6 2007/11/13 23:37:28 sybreon
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// Updated simulation to also check BRI 0x00 instruction.
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//
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// Revision 1.5 2007/11/09 20:51:53 sybreon
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// Added GET/PUT support through a FSL bus.
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//
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// Revision 1.4 2007/11/08 14:18:00 sybreon
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// Parameterised optional components.
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//
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// Revision 1.3 2007/11/05 10:59:31 sybreon
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// Added random seed for simulation.
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//
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// Revision 1.2 2007/11/02 19:16:10 sybreon
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// Added interrupt simulation.
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// Changed "human readable" simulation output.
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//
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// Revision 1.1 2007/11/02 03:25:45 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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`define AEMB_SIMULATION_KERNEL
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`define AEMB_SIMULATION_KERNEL
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module edk32 ();
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module edk32 ();
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Line 178... |
integer rnd;
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integer rnd;
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always @(posedge sys_clk_i) begin
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always @(posedge sys_clk_i) begin
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// Interrupt Monitors
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// Interrupt Monitors
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if (!dut.rMSR_IE) begin
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if (!dut.cpu.rMSR_IE) begin
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rnd = $random % 30;
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rnd = $random % 30;
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inttime = $stime + 1000 + (rnd*rnd * 10);
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inttime = $stime + 1000 + (rnd*rnd * 10);
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end
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end
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if ($stime > inttime) begin
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if ($stime > inttime) begin
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sys_int_i = 1;
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sys_int_i = 1;
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Line 191... |
if (($stime > inttime + 500) && !svc) begin
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if (($stime > inttime + 500) && !svc) begin
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$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
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$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
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$finish;
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$finish;
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end
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end
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if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
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if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
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if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
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if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin
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svc = 1;
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svc = 1;
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//$display("\nLATENCY: ", ($stime - inttime)/10);
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//$display("\nLATENCY: ", ($stime - inttime)/10);
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end
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end
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// Pass/Fail Monitors
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// Pass/Fail Monitors
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end
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end
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end // always @ (posedge sys_clk_i)
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end // always @ (posedge sys_clk_i)
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// INTERNAL WIRING ////////////////////////////////////////////////////
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// INTERNAL WIRING ////////////////////////////////////////////////////
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aeMB_edk32 #(16,16)
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aeMB_sim #(16,16)
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dut (
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dut (
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.sys_int_i(sys_int_i),
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.sys_int_i(sys_int_i),
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.dwb_ack_i(dwb_ack_i),
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.dwb_ack_i(dwb_ack_i),
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.dwb_stb_o(dwb_stb_o),
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.dwb_stb_o(dwb_stb_o),
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.dwb_adr_o(dwb_adr_o),
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.dwb_adr_o(dwb_adr_o),
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.sys_rst_i(sys_rst_i)
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.sys_rst_i(sys_rst_i)
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);
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);
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endmodule // edk32
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endmodule // edk32
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No newline at end of file
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No newline at end of file
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/*
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$Log: not supported by cvs2svn $
|
|
Revision 1.11 2007/12/11 00:44:31 sybreon
|
|
Modified for AEMB2
|
|
|
|
Revision 1.10 2007/11/30 17:08:30 sybreon
|
|
Moved simulation kernel into code.
|
|
|
|
Revision 1.9 2007/11/20 18:36:00 sybreon
|
|
Removed unnecessary byte acrobatics with VMEM data.
|
|
|
|
Revision 1.8 2007/11/18 19:41:45 sybreon
|
|
Minor simulation fixes.
|
|
|
|
Revision 1.7 2007/11/14 22:11:41 sybreon
|
|
Added posedge/negedge bus interface.
|
|
Modified interrupt test system.
|
|
|
|
Revision 1.6 2007/11/13 23:37:28 sybreon
|
|
Updated simulation to also check BRI 0x00 instruction.
|
|
|
|
Revision 1.5 2007/11/09 20:51:53 sybreon
|
|
Added GET/PUT support through a FSL bus.
|
|
|
|
Revision 1.4 2007/11/08 14:18:00 sybreon
|
|
Parameterised optional components.
|
|
|
|
Revision 1.3 2007/11/05 10:59:31 sybreon
|
|
Added random seed for simulation.
|
|
|
|
Revision 1.2 2007/11/02 19:16:10 sybreon
|
|
Added interrupt simulation.
|
|
Changed "human readable" simulation output.
|
|
|
|
Revision 1.1 2007/11/02 03:25:45 sybreon
|
|
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
|
|
Fixed various minor data hazard bugs.
|
|
Code compatible with -O0/1/2/3/s generated code.
|
|
*/
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No newline at end of file
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No newline at end of file
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