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/* $Id: edk62.v,v 1.2 2008-04-27 16:28:19 sybreon Exp $
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/* $Id: edk62.v,v 1.3 2008-05-01 08:33:20 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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localparam AEMB_IDX = 6;
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localparam AEMB_IDX = 6;
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localparam AEMB_HTX = 1;
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localparam AEMB_HTX = 1;
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localparam AEMB_BSF = 1;
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localparam AEMB_BSF = 1;
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localparam AEMB_MUL = 1;
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localparam AEMB_MUL = 1;
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localparam AEMB_XSL = 1;
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localparam AEMB_XSL = 1;
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localparam AEMB_DIV = 0;
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localparam AEMB_FPU = 0;
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/*AUTOREGINPUT*/
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/*AUTOREGINPUT*/
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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reg dwb_ack_i; // To uut of aeMB2_edk62.v
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reg dwb_ack_i; // To uut of aeMB2_edk62.v
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reg iwb_ack_i; // To uut of aeMB2_edk62.v
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reg iwb_ack_i; // To uut of aeMB2_edk62.v
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reg sys_clk_i; // To uut of aeMB2_edk62.v
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reg sys_clk_i; // To uut of aeMB2_edk62.v
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reg sys_ena_i; // To uut of aeMB2_edk62.v
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reg sys_ena_i; // To uut of aeMB2_edk62.v
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reg sys_int_i; // To uut of aeMB2_edk62.v
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reg sys_rst_i; // To uut of aeMB2_edk62.v
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reg sys_rst_i; // To uut of aeMB2_edk62.v
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reg xwb_ack_i; // To uut of aeMB2_edk62.v
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reg xwb_ack_i; // To uut of aeMB2_edk62.v
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// End of automatics
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// End of automatics
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always #5 sys_clk_i <= !sys_clk_i;
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always #5 sys_clk_i <= !sys_clk_i;
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`endif
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`endif
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sys_clk_i = 0;
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sys_clk_i = 0;
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sys_rst_i = 1;
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sys_rst_i = 1;
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sys_ena_i = 1;
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sys_ena_i = 1;
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sys_int_i = 1;
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xwb_ack_i = 0;
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xwb_ack_i = 0;
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#50 sys_rst_i = 0;
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#50 sys_rst_i = 0;
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#4000000 $displayh("\n*** TIMEOUT ", $stime, " ***"); $finish;
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#4000000 $displayh("\n*** TIMEOUT ", $stime, " ***"); $finish;
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wire dwb_wre_o; // From uut of aeMB2_edk62.v
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wire dwb_wre_o; // From uut of aeMB2_edk62.v
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wire [AEMB_IWB-1:2] iwb_adr_o; // From uut of aeMB2_edk62.v
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wire [AEMB_IWB-1:2] iwb_adr_o; // From uut of aeMB2_edk62.v
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wire iwb_cyc_o; // From uut of aeMB2_edk62.v
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wire iwb_cyc_o; // From uut of aeMB2_edk62.v
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wire [3:0] iwb_sel_o; // From uut of aeMB2_edk62.v
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wire [3:0] iwb_sel_o; // From uut of aeMB2_edk62.v
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wire iwb_stb_o; // From uut of aeMB2_edk62.v
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wire iwb_stb_o; // From uut of aeMB2_edk62.v
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wire iwb_tag_o; // From uut of aeMB2_edk62.v
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wire iwb_wre_o; // From uut of aeMB2_edk62.v
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wire iwb_wre_o; // From uut of aeMB2_edk62.v
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wire [AEMB_XWB-1:2] xwb_adr_o; // From uut of aeMB2_edk62.v
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wire [AEMB_XWB-1:2] xwb_adr_o; // From uut of aeMB2_edk62.v
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wire xwb_cyc_o; // From uut of aeMB2_edk62.v
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wire xwb_cyc_o; // From uut of aeMB2_edk62.v
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wire [31:0] xwb_dat_o; // From uut of aeMB2_edk62.v
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wire [31:0] xwb_dat_o; // From uut of aeMB2_edk62.v
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wire [3:0] xwb_sel_o; // From uut of aeMB2_edk62.v
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wire [3:0] xwb_sel_o; // From uut of aeMB2_edk62.v
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// SPECIAL PORTS
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// SPECIAL PORTS
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if (dwb_wre_o & dwb_stb_o & dwb_ack_i) begin
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if (dwb_wre_o & dwb_stb_o & dwb_ack_i) begin
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case ({dwb_adr_o,2'o0})
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case ({dwb_adr_o,2'o0})
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32'hFFFFFFD0: $displayh(dwb_dat_o);
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32'hFFFFFFD0: $displayh(dwb_dat_o);
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32'hFFFFFFC0: $write("%c",dwb_dat_o[31:24]);
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32'hFFFFFFC0: $write("%c",dwb_dat_o[31:24]);
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32'hFFFFFFE0: sys_int_i <= #1 !sys_int_i;
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endcase // case ({dwb_adr_o,2'o0})
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endcase // case ({dwb_adr_o,2'o0})
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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.AEMB_XWB (AEMB_XWB),
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.AEMB_XWB (AEMB_XWB),
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.AEMB_ICH (AEMB_ICH),
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.AEMB_ICH (AEMB_ICH),
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.AEMB_IDX (AEMB_IDX),
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.AEMB_IDX (AEMB_IDX),
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.AEMB_BSF (AEMB_BSF),
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.AEMB_BSF (AEMB_BSF),
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.AEMB_MUL (AEMB_MUL),
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.AEMB_MUL (AEMB_MUL),
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.AEMB_XSL (AEMB_XSL),
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.AEMB_DIV (AEMB_DIV),
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.AEMB_HTX (AEMB_HTX))
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.AEMB_FPU (AEMB_FPU))
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uut
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uut
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.dwb_adr_o (dwb_adr_o[AEMB_DWB-1:2]),
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.dwb_adr_o (dwb_adr_o[AEMB_DWB-1:2]),
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.dwb_cyc_o (dwb_cyc_o),
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.dwb_cyc_o (dwb_cyc_o),
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.dwb_wre_o (dwb_wre_o),
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.dwb_wre_o (dwb_wre_o),
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.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]),
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.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]),
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.iwb_cyc_o (iwb_cyc_o),
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.iwb_cyc_o (iwb_cyc_o),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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.iwb_tag_o (iwb_tag_o),
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.iwb_wre_o (iwb_wre_o),
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.iwb_wre_o (iwb_wre_o),
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.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]),
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.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]),
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.xwb_cyc_o (xwb_cyc_o),
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.xwb_cyc_o (xwb_cyc_o),
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.xwb_dat_o (xwb_dat_o[31:0]),
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.xwb_dat_o (xwb_dat_o[31:0]),
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.xwb_sel_o (xwb_sel_o[3:0]),
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.xwb_sel_o (xwb_sel_o[3:0]),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.sys_clk_i (sys_clk_i),
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.sys_clk_i (sys_clk_i),
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.sys_ena_i (sys_ena_i),
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.sys_ena_i (sys_ena_i),
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.sys_int_i (sys_int_i),
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.sys_rst_i (sys_rst_i),
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.sys_rst_i (sys_rst_i),
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.xwb_ack_i (xwb_ack_i),
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.xwb_ack_i (xwb_ack_i),
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.xwb_dat_i (xwb_dat_i[31:0]));
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.xwb_dat_i (xwb_dat_i[31:0]));
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endmodule // edk62
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endmodule // edk62
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2008/04/27 16:28:19 sybreon
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// Fixed minor typos.
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//
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// Revision 1.1 2008/04/26 18:09:16 sybreon
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// Revision 1.1 2008/04/26 18:09:16 sybreon
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// initial import
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// initial import
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//
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//
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// Local Variables:
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// Local Variables:
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