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[/] [aemb/] [trunk/] [sim/] [verilog/] [edk62.v] - Diff between revs 157 and 164
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| Rev 157 |
Rev 164 |
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/* $Id: edk62.v,v 1.3 2008-05-01 08:33:20 sybreon Exp $
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/* $Id: edk62.v,v 1.4 2008-05-30 14:02:59 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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Simulation Test Bench
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Simulation Test Bench
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@file edk62.v
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@file edk62.v
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*/
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*/
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`include "random.v"
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module edk62();
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module edk62();
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localparam AEMB_DWB = 18;
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localparam AEMB_DWB = 18;
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localparam AEMB_XWB = 5;
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localparam AEMB_XWB = 5;
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localparam AEMB_IWB = 18;
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localparam AEMB_IWB = 18;
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localparam AEMB_ICH = 11;
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localparam AEMB_ICH = 11;
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`ifdef VCD_DUMP
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`ifdef VCD_DUMP
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$dumpfile ("dump.vcd");
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$dumpfile ("dump.vcd");
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$dumpvars (1,uut);
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$dumpvars (1,uut);
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`endif
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`endif
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sys_clk_i = 0;
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sys_clk_i = $random(`randseed);
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sys_rst_i = 1;
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sys_rst_i = 1;
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sys_ena_i = 1;
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sys_ena_i = 1;
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sys_int_i = 1;
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sys_int_i = 1;
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xwb_ack_i = 0;
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xwb_ack_i = 0;
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.xwb_dat_i (xwb_dat_i[31:0]));
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.xwb_dat_i (xwb_dat_i[31:0]));
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endmodule // edk62
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endmodule // edk62
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2008/05/01 08:33:20 sybreon
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// Added interrupt capability.
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//
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// Revision 1.2 2008/04/27 16:28:19 sybreon
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// Revision 1.2 2008/04/27 16:28:19 sybreon
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// Fixed minor typos.
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// Fixed minor typos.
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//
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//
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// Revision 1.1 2008/04/26 18:09:16 sybreon
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// Revision 1.1 2008/04/26 18:09:16 sybreon
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// initial import
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// initial import
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