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/* $Id: msr.hh,v 1.3 2008-04-11 12:24:12 sybreon Exp $
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/* $Id: msr.hh,v 1.4 2008-04-11 15:53:03 sybreon Exp $
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**
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**
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** AEMB2 HI-PERFORMANCE CPU
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** AEMB2 HI-PERFORMANCE CPU
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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const int MSR_FSL = 0x00000010; ///< FSL Error
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const int MSR_FSL = 0x00000010; ///< FSL Error
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const int MSR_ICE = 0x00000020; ///< Instruction Cache Enable
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const int MSR_ICE = 0x00000020; ///< Instruction Cache Enable
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const int MSR_DZ = 0x00000040; ///< Division by Zero
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const int MSR_DZ = 0x00000040; ///< Division by Zero
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const int MSR_DCE = 0x00000080; ///< Data Cache Enable
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const int MSR_DCE = 0x00000080; ///< Data Cache Enable
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const int MSR_TXE = 0x00000100; ///< thread enable
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const int MSR_HTE = 0x10000000; ///< Hardware Threads Enable
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const int MSR_PHA = 0x00000200; ///< thread phase
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const int MSR_HTP = 0x20000000; ///< Hardware Thread Phase
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const int MSR_HTE = 0x00000400; ///< hardware thread capable
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const int MSR_HTX = 0x40000000; ///< Hardware Threads Extension
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/**
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/**
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Read the value of the MSR register
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Read the value of the MSR register
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@return register contents
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@return register contents
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*/
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*/
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};
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};
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#endif
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#endif
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.3 2008/04/11 12:24:12 sybreon
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added cache controls
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Revision 1.2 2008/04/11 11:48:37 sybreon
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Revision 1.2 2008/04/11 11:48:37 sybreon
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added interrupt controls (may need to be factorised out)
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added interrupt controls (may need to be factorised out)
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Revision 1.1 2008/04/09 19:48:37 sybreon
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Revision 1.1 2008/04/09 19:48:37 sybreon
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Added new C++ files
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Added new C++ files
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