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[/] [aemb/] [trunk/] [sw/] [cc/] [aemb/] [msr.hh] - Diff between revs 121 and 137
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Rev 137 |
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/* $Id: msr.hh,v 1.5 2008-04-20 16:35:53 sybreon Exp $
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/* $Id: msr.hh,v 1.6 2008-04-26 18:05:22 sybreon Exp $
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**
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**
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** AEMB2 HI-PERFORMANCE CPU
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** AEMB2 HI-PERFORMANCE CPU
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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*/
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*/
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#ifndef AEMB_MSR_HH
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#ifndef AEMB_MSR_HH
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#define AEMB_MSR_HH
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#define AEMB_MSR_HH
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#ifdef __cplusplus
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namespace aemb {
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namespace aemb {
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#endif
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const int MSR_BE = 0x00000001; ///< Buslock Enable
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const int MSR_BE = 0x00000001; ///< Buslock Enable
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const int MSR_IE = 0x00000002; ///< Interrupt Enable
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const int MSR_IE = 0x00000002; ///< Interrupt Enable
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const int MSR_C = 0x00000004; ///< Arithmetic Carry
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const int MSR_C = 0x00000004; ///< Arithmetic Carry
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const int MSR_BIP = 0x00000008; ///< Break in Progress
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const int MSR_BIP = 0x00000008; ///< Break in Progress
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inline void disableInstCache()
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inline void disableInstCache()
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{
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{
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putMSR(getMSR() & ~MSR_ICE);
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putMSR(getMSR() & ~MSR_ICE);
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}
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}
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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#endif
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.5 2008/04/20 16:35:53 sybreon
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Added C/C++ compatible #ifdef statements
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Revision 1.4 2008/04/11 15:53:03 sybreon
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Revision 1.4 2008/04/11 15:53:03 sybreon
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changed MSR bits
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changed MSR bits
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Revision 1.3 2008/04/11 12:24:12 sybreon
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Revision 1.3 2008/04/11 12:24:12 sybreon
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added cache controls
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added cache controls
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