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/* $Id: msr.hh,v 1.8 2008-04-27 16:33:42 sybreon Exp $
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/* $Id: msr.hh,v 1.9 2008-04-28 20:29:15 sybreon Exp $
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**
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**
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** AEMB2 HI-PERFORMANCE CPU
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** AEMB2 HI-PERFORMANCE CPU
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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These functions provide read/write access to the Machine Status
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These functions provide read/write access to the Machine Status
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Register. It also contains the bit definitions of the register.
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Register. It also contains the bit definitions of the register.
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*/
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*/
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#ifndef AEMB_MSR_HH
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#ifndef _AEMB_MSR_HH
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#define AEMB_MSR_HH
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#define _AEMB_MSR_HH
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// STANDARD BITS
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// STANDARD BITS
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#define MSR_BE (1 << 0) ///< Buslock Enable
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#define AEMB_MSR_BE (1 << 0) ///< Buslock Enable
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#define MSR_IE (1 << 1) ///< Interrupt Enable
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#define AEMB_MSR_IE (1 << 1) ///< Interrupt Enable
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#define MSR_C (1 << 2) ///< Arithmetic Carry
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#define AEMB_MSR_C (1 << 2) ///< Arithmetic Carry
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#define MSR_BIP (1 << 3) ///< Break in Progress
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#define AEMB_MSR_BIP (1 << 3) ///< Break in Progress
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#define MSR_ICE (1 << 5) ///< Instruction Cache Enable
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#define AEMB_MSR_ITE (1 << 5) ///< Instruction Cache Enable
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#define MSR_DZ (1 << 6) ///< Division by Zero
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#define AEMB_MSR_DZ (1 << 6) ///< Division by Zero
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#define MSR_DCE (1 << 7) ///< Data Cache Enable
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#define AEMB_MSR_DTE (1 << 7) ///< Data Cache Enable
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// CUSTOM BITS
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// CUSTOM BITS
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#define MSR_MTX (1 << 4) ///< Hardware Mutex
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#define AEMB_MSR_MTX (1 << 4) ///< Hardware Mutex
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#define MSR_PHA (1 << 29) ///< Hardware Thread Phase
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#define AEMB_MSR_PHA (1 << 29) ///< Hardware Thread Phase
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#define MSR_HTX (1 << 30) ///< Hardware Threads Extension
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#define AEMB_MSR_HTX (1 << 30) ///< Hardware Threads Extension
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#define MSR_CC (1 << 31) ///< Carry Copy
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#define AEMB_MSR_CC (1 << 31) ///< Carry Copy
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#ifdef __cplusplus
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#ifdef __cplusplus
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namespace aemb {
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extern "C" {
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#endif
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#endif
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/**
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/**
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Read the value of the MSR register
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Read the value of the MSR register
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@return register contents
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@return register contents
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*/
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*/
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inline int getMSR()
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inline int aembGetMSR()
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{
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{
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int rmsr;
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int rmsr;
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asm volatile ("mfs %0, rmsr":"=r"(rmsr));
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asm volatile ("mfs %0, rmsr":"=r"(rmsr));
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return rmsr;
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return rmsr;
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}
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}
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/**
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/**
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Write a value to the MSR register
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Write a value to the MSR register
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@param rmsr value to write
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@param rmsr value to write
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*/
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*/
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inline void putMSR(int rmsr)
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inline void aembPutMSR(int rmsr)
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{
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{
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asm volatile ("mts rmsr, %0"::"r"(rmsr));
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asm volatile ("mts rmsr, %0"::"r"(rmsr));
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}
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}
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/**
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/**
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Read and clear the MSR
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Read and clear the MSR
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@param rmsk clear mask
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@param rmsk clear mask
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@return msr value
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@return msr value
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*/
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*/
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inline int clrMSR(const short rmsk)
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inline int aembClrMSR(const short rmsk)
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{
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{
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int tmp;
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int tmp;
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//asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk):"memory");
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//asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk):"memory");
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return tmp;
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return tmp;
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}
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}
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Read and set the MSR
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Read and set the MSR
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@param rmsk set mask
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@param rmsk set mask
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@return msr value
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@return msr value
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*/
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*/
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inline int setMSR(const short rmsk)
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inline int aembSetMSR(const short rmsk)
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{
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{
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int tmp;
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int tmp;
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//asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk):"memory");
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//asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk):"memory");
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return tmp;
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return tmp;
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}
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}
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/** Enable global interrupts */
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/** Enable global interrupts */
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inline void enableInterrupts()
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inline int aembEnableInterrupts()
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{
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{
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asm volatile ("msrset r0, %0"::"K"(MSR_IE):"memory");
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int msr;
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
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return msr;
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}
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}
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/** Disable global interrupts */
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/** Disable global interrupts */
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inline void disableInterrupts()
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inline int aembDisableInterrupts()
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{
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{
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asm volatile ("msrclr r0, %0"::"K"(MSR_IE));
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int msr;
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
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return msr;
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}
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}
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/** Enable data caches */
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/** Enable data caches */
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inline void enableDataCache()
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inline int aembEnableDataTag()
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{
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{
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asm volatile ("msrset r0, %0"::"K"(MSR_DCE));
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int msr;
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
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return msr;
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}
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}
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/** Disable data caches */
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/** Disable data caches */
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inline void disableDataCache()
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inline int aembDisableDataTag()
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{
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{
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asm volatile ("msrclr r0, %0"::"K"(MSR_DCE));
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int msr;
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
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return msr;
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}
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}
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/** Enable inst caches */
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/** Enable inst caches */
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inline void enableInstCache()
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inline int aembEnableInstTag()
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{
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{
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asm volatile ("msrset r0, %0"::"K"(MSR_ICE));
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int msr;
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
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return msr;
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}
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}
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/** Disable inst caches */
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/** Disable inst caches */
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inline void disableInstCache()
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inline int aembDisableInstTag()
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{
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{
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asm volatile ("msrclr r0, %0"::"K"(MSR_ICE));
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int msr;
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
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return msr;
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}
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}
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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#endif
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#endif
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.8 2008/04/27 16:33:42 sybreon
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License change to GPL3.
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Revision 1.7 2008/04/26 19:31:35 sybreon
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Revision 1.7 2008/04/26 19:31:35 sybreon
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Made headers C compatible.
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Made headers C compatible.
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Revision 1.6 2008/04/26 18:05:22 sybreon
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Revision 1.6 2008/04/26 18:05:22 sybreon
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Minor cosmetic changes.
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Minor cosmetic changes.
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