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/* $Id: thread.hh,v 1.3 2008-04-11 15:53:24 sybreon Exp $
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/* $Id: thread.hh,v 1.4 2008-04-12 14:07:26 sybreon Exp $
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**
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**
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** AEMB2 HI-PERFORMANCE CPU
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** AEMB2 HI-PERFORMANCE CPU
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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required as the threads are hardware. This can be implemented using
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required as the threads are hardware. This can be implemented using
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a specialised add/sub/load register.
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a specialised add/sub/load register.
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*/
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*/
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class semaphore {
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class semaphore {
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private:
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volatile int _sem; ///< Semaphore in Memory
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volatile int _sem; ///< Semaphore in Memory
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public:
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public:
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/**
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/**
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Preload the semaphore
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Preload the semaphore
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@param pval preload value
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@param pval preload value
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inline void wait() { _sem--; while (_sem < 0); } // block while
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inline void wait() { _sem--; while (_sem < 0); } // block while
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// semaphore is
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// semaphore is
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// negative
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// negative
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};
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};
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semaphore __mutex_rendezvous0(0); ///< internal rendezvous mutex
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semaphore __mutex_rendezvous1(1); ///< internal rendezvous mutex
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/**
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Implements a simple rendezvous mechanism
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*/
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void rendezvous()
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{
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if (isThread1())
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{
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__mutex_rendezvous0.wait();
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__mutex_rendezvous1.signal();
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}
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else
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{
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__mutex_rendezvous0.signal();
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__mutex_rendezvous1.wait();
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}
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}
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}
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}
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#endif
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#endif
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.3 2008/04/11 15:53:24 sybreon
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changed MSR bits
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Revision 1.2 2008/04/11 11:34:30 sybreon
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Revision 1.2 2008/04/11 11:34:30 sybreon
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changed semaphore case
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changed semaphore case
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Revision 1.1 2008/04/09 19:48:37 sybreon
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Revision 1.1 2008/04/09 19:48:37 sybreon
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Added new C++ files
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Added new C++ files
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