URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [rtl/] [ram_16x64.v] - Diff between revs 5 and 8

Rev 5	Rev 8
Line 28...	Line 28...
`begin`	`begin`
`if (wr)`	`if (wr)`
`mem[wr_addr] <= wr_data;`	`mem[wr_addr] <= wr_data;`
`end`	`end`

`//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI`

`reg [3:0] srd_addr;`	`reg [3:0] srd_addr;`

`always @ (posedge clk)`	`always @ (posedge clk)`
`begin`	`begin`
`if (rd)`	`if (rd)`
`srd_addr <= rd_addr;`	`srd_addr <= rd_addr;`
`end`	`end`

`assign rd_data = mem[srd_addr];`	`assign rd_data = mem[srd_addr];`

`//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI`

`// always @ (posedge clk)`
`// begin`
`// if (rd)`
`// rd_data <= mem[rd_addr];`
`// end`

`//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`