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Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [rtl/] [sbox.v] - Diff between revs 5 and 7

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Rev 5 Rev 7
Line 12... Line 12...
////      - Luo Dongjun,   dongjun_luo@hotmail.com                ////
////      - Luo Dongjun,   dongjun_luo@hotmail.com                ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module sbox(
module sbox(
        clk,
        clk,
        reset_n,
        reset,
        enable,
        enable,
        din,
        din,
        ende,
        ende,
        en_dout,
        en_dout,
        de_dout);
        de_dout);
 
 
input           clk;
input           clk;
input           reset_n;
input           reset;
input           enable;
input           enable;
input   [7:0]    din;
input   [7:0]    din;
input           ende;  //0: encryption;  1: decryption
input           ende;  //0: encryption;  1: decryption
output  [7:0]    en_dout;
output  [7:0]    en_dout;
output  [7:0]    de_dout;
output  [7:0]    de_dout;
Line 37... Line 37...
// GF(256) to GF(16) transformation
// GF(256) to GF(16) transformation
assign first_matrix_in[7:0] = ende ? INV_AFFINE(din[7:0]): din[7:0];
assign first_matrix_in[7:0] = ende ? INV_AFFINE(din[7:0]): din[7:0];
assign first_matrix_out[7:0] = GF256_TO_GF16(first_matrix_in[7:0]);
assign first_matrix_out[7:0] = GF256_TO_GF16(first_matrix_in[7:0]);
 
 
// pipeline 1
// pipeline 1
always @ (posedge clk or negedge reset_n)
always @ (posedge clk or posedge reset)
begin
begin
        if (!reset_n)
        if (reset)
                first_matrix_out_L[7:0] <= 8'b0;
                first_matrix_out_L[7:0] <= 8'b0;
        else if (enable)
        else if (enable)
                first_matrix_out_L[7:0] <= first_matrix_out[7:0];
                first_matrix_out_L[7:0] <= first_matrix_out[7:0];
end
end
 
 
Line 79... Line 79...
// results
// results
assign p_new[3:0] = MUL(sumpq[3:0],inv_sump2q2[3:0]);
assign p_new[3:0] = MUL(sumpq[3:0],inv_sump2q2[3:0]);
assign q_new[3:0] = MUL(q[3:0],inv_sump2q2[3:0]);
assign q_new[3:0] = MUL(q[3:0],inv_sump2q2[3:0]);
 
 
// pipeline 2
// pipeline 2
always @ (posedge clk or negedge reset_n)
always @ (posedge clk or posedge reset)
begin
begin
        if (!reset_n)
        if (reset)
                {p_new_L[3:0],q_new_L[3:0]} <= 8'b0;
                {p_new_L[3:0],q_new_L[3:0]} <= 8'b0;
        else if (enable)
        else if (enable)
                {p_new_L[3:0],q_new_L[3:0]} <= {p_new[3:0],q_new[3:0]};
                {p_new_L[3:0],q_new_L[3:0]} <= {p_new[3:0],q_new[3:0]};
end
end
 
 

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