| Line 71... |
Line 71... |
signal clk: std_logic; -- clock
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signal clk: std_logic; -- clock
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signal plaintext: datablock;
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signal plaintext: datablock;
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signal key: datablock;
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signal key: datablock;
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signal cipher: datablock;
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signal cipher: datablock;
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signal rst: std_logic; -- reset input
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signal rst: std_logic; -- reset input
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signal op_start: std_logic; -- signal that simulation ended
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signal op_start: std_logic; -- signal that output started
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signal sim_end: std_logic := '0'; -- signal that simulation ended
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constant clk_period: time := 10 ns;
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constant clk_period: time := 10 ns;
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component aes_top is
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component aes_top is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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| Line 96... |
Line 97... |
ciphertext_o => cipher
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ciphertext_o => cipher
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);
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);
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-- Generate clock
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-- Generate clock
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gen_clk: process
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gen_clk: process
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begin
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begin
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if(sim_end = '0') then
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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else
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wait;
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end if;
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end process;
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end process;
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-- Generate Reset
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-- Generate Reset
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gen_rst: process
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gen_rst: process
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begin
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begin
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rst <= '1';
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rst <= '1';
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| Line 114... |
Line 119... |
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-- generate the inputs and check against expected output
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-- generate the inputs and check against expected output
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gen_in: process
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gen_in: process
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file testfile: text open read_mode is "../src/vectors.dat";
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file testfile: text open read_mode is "../src/vectors.dat";
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variable line_in: line;
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variable line_in: line;
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variable plaintext_byte, key_byte: std_logic_vector(7 downto 0);
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variable plaintext_block, key_block: std_logic_vector(127 downto 0);
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begin
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begin
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if(endfile(testfile)) then
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if(endfile(testfile)) then
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file_close(testfile);
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file_close(testfile);
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wait;
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wait;
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end if;
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end if;
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readline(testfile, line_in);
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readline(testfile, line_in);
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hread(line_in, plaintext_block);
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hread(line_in, key_block);
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for i in 3 downto 0 loop
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for i in 3 downto 0 loop
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for j in 3 downto 0 loop
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for j in 3 downto 0 loop
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hread(line_in, plaintext_byte);
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plaintext(3-j,3-i) <= plaintext_block((i*32 + j*8 + 7) downto (i*32 + j*8));
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plaintext(3-j,3-i) <= plaintext_byte;
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end loop;
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end loop;
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end loop;
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end loop;
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for i in 3 downto 0 loop
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for i in 3 downto 0 loop
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for j in 3 downto 0 loop
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for j in 3 downto 0 loop
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hread(line_in, key_byte);
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key(3-j,3-i) <= key_block((i*32 + j*8 + 7) downto (i*32 + j*8));
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key(3-j,3-i) <= key_byte;
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end loop;
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end loop;
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end loop;
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end loop;
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wait for clk_period;
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wait for clk_period;
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end process;
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end process;
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| Line 149... |
Line 154... |
wait;
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wait;
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end process;
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end process;
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-- Compare output with actual output file
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-- Compare output with actual output file
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op_chk: process
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op_chk: process
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file chkfile: text open read_mode is "../src/cipher.dat";
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file opfile: text open read_mode is "../src/cipher.dat";
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file opfile: text open write_mode is "../log/output.log";
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file logfile: text open write_mode is "../log/output.log";
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variable line_in, line_out_file, line_out: line;
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variable line_in, line_out, line_out_file: line;
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variable exp_cipher_byte: std_logic_vector(7 downto 0);
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variable exp_cipher_block: std_logic_vector(127 downto 0);
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variable succeded: boolean;
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variable succeded: boolean;
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variable all_ok: boolean := true;
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begin
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begin
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-- if required cycles have passed
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-- if required cycles have passed
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if(op_start = '1') then
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if(op_start = '1') then
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if(endfile(chkfile)) then -- end of simulation
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if(endfile(opfile)) then -- end of simulation
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file_close(chkfile);
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file_close(opfile);
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if(all_ok = true) then
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write(line_out, string'("OK"));
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writeline(OUTPUT, line_out);
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write(line_out_file, string'("OK"));
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writeline(logfile, line_out_file);
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else
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write(line_out, string'("FAIL"));
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writeline(OUTPUT, line_out);
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write(line_out_file, string'("FAIL"));
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writeline(logfile, line_out_file);
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end if;
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sim_end <= '1';
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wait;
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wait;
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end if;
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end if;
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succeded := true;
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succeded := true;
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readline(chkfile, line_in); -- read in one expected result
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readline(opfile, line_in); -- read in one expected result
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hread(line_in, exp_cipher_block); -- read in one byte
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for i in 3 downto 0 loop
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for i in 3 downto 0 loop
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for j in 3 downto 0 loop
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for j in 3 downto 0 loop
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hread(line_in, exp_cipher_byte); -- read in one byte
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if(exp_cipher_block((i*32 + j*8 + 7) downto (i*32 + j*8)) /= cipher(3-j,3-i)) then
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if(exp_cipher_byte /= cipher(3-j,3-i)) then
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succeded := false; -- check failed
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succeded := false; -- check failed
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all_ok := false;
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end if;
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end if;
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end loop;
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end loop;
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end loop;
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end loop;
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-- writing the output line
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-- writing the output line
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for i in 3 downto 0 loop
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for i in 3 downto 0 loop
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for j in 3 downto 0 loop
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for j in 3 downto 0 loop
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hwrite(line_out_file, cipher(3-j,3-i));
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hwrite(line_out, cipher(3-j,3-i));
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hwrite(line_out, cipher(3-j,3-i));
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hwrite(line_out_file, cipher(3-j,3-i));
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end loop;
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end loop;
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end loop;
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end loop;
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write(line_out_file, ' ');
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write(line_out, ' ');
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write(line_out, ' ');
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write(line_out_file, ' ');
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-- writing the comparison result
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-- writing the comparison result
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write(line_out_file, succeded);
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write(line_out, succeded);
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write(line_out, succeded);
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writeline(opfile, line_out_file);
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writeline(OUTPUT, line_out);
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writeline(OUTPUT, line_out);
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write(line_out_file, succeded);
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writeline(logfile, line_out_file);
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end if;
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end if;
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wait for clk_period;
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wait for clk_period;
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end process;
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end process;
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end rtl;
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end rtl;
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No newline at end of file
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No newline at end of file
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