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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Pipelined Aes IP Core ----
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---- ----
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---- This file is part of the Pipelined AES project ----
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---- http://www.opencores.org/cores/aes_pipe/ ----
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---- ----
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---- Description ----
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---- Implementation of AES IP core according to ----
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---- FIPS PUB 197 specification document. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author: ----
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---- - Subhasis Das, subhasis256@gmail.com ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http:--www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Project: AESFast
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-- Author: Subhasis
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Last Modified: 25/03/10
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-- Email: subhasis256@gmail.com
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-- Email: subhasis256@gmail.com
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--
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--
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-- TODO: Test with NIST test vectors
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-- TODO: Test with NIST test vectors
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------------------------------------------------------
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------------------------------------------------------
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--
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--
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-- Description: Testbench for AESFast
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-- Description: Testbench for AESFast
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-- Takes in data and keys from ../src/vectors.dat
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-- Takes in true output values from ../src/cipher.dat
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-- Writes all the output to ../log/output.log
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------------------------------------------------------
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------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_textio.all;
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use IEEE.std_logic_unsigned.all;
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use std.textio.all;
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library work;
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library work;
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use work.aes_pkg.all;
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use work.aes_pkg.all;
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entity tb_aes is
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entity tb_aes is
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end tb_aes;
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end tb_aes;
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architecture rtl of tb_aes is
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architecture rtl of tb_aes is
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signal clk: std_logic;
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signal clk: std_logic; -- clock
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signal plaintext: datablock;
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signal plaintext: datablock;
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signal key: datablock;
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signal key: datablock;
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signal cipher: datablock;
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signal cipher: datablock;
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signal start: std_logic := '0';
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signal rst: std_logic; -- reset input
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signal done: std_logic;
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signal op_start: std_logic; -- signal that simulation ended
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constant clk_period: time := 10 ns;
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component aes_top is
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component aes_top is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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plaintext_i: in datablock;
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plaintext_i: in datablock;
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keyblock_i: in datablock;
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keyblock_i: in datablock;
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ciphertext_o: out datablock
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ciphertext_o: out datablock
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);
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);
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end component;
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end component;
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begin
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begin
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g0: for i in 3 downto 0 generate
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-- The wiring of the top module
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g1: for j in 3 downto 1 generate
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DUT: aes_top port map(
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plaintext(i,j) <= X"00";
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key(i,j) <= X"00";
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end generate;
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end generate;
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plaintext(3,0) <= X"00";
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plaintext(2,0) <= X"00";
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plaintext(1,0) <= X"00";
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key(3,0) <= X"00";
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key(2,0) <= X"00";
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key(1,0) <= X"00";
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key(0,0) <= X"00";
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proc0: aes_top port map(
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clk_i => clk,
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clk_i => clk,
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rst_i => rst,
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plaintext_i => plaintext,
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plaintext_i => plaintext,
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keyblock_i => key,
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keyblock_i => key,
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ciphertext_o => cipher
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ciphertext_o => cipher
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);
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);
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-- Generate clock
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gen_clk: process
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gen_clk: process
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begin
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begin
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wait for 10 ns;
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clk <= '1';
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clk <= '1';
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wait for 10 ns;
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wait for clk_period/2;
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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end process;
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-- Generate Reset
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gen_rst: process
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begin
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rst <= '1';
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wait for clk_period/2; -- generate reset
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rst <= '0';
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wait;
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end process;
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end process;
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-- generate the inputs and check against expected output
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gen_in: process
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gen_in: process
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file testfile: text open read_mode is "../src/vectors.dat";
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variable line_in: line;
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variable plaintext_byte, key_byte: std_logic_vector(7 downto 0);
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begin
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if(endfile(testfile)) then
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file_close(testfile);
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wait;
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end if;
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readline(testfile, line_in);
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for i in 3 downto 0 loop
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for j in 3 downto 0 loop
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hread(line_in, plaintext_byte);
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plaintext(3-j,3-i) <= plaintext_byte;
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end loop;
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end loop;
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for i in 3 downto 0 loop
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for j in 3 downto 0 loop
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hread(line_in, key_byte);
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key(3-j,3-i) <= key_byte;
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end loop;
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end loop;
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wait for clk_period;
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end process;
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-- Generate a signal to indicate that valid output has begun
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op_begin: process
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begin
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wait for 30*clk_period;
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wait for clk_period/2;
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op_start <= '1';
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wait;
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end process;
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-- Compare output with actual output file
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op_chk: process
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file chkfile: text open read_mode is "../src/cipher.dat";
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file opfile: text open write_mode is "../log/output.log";
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variable line_in, line_out_file, line_out: line;
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variable exp_cipher_byte: std_logic_vector(7 downto 0);
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variable succeded: boolean;
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begin
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begin
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wait for 25 ns;
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-- if required cycles have passed
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plaintext(0,0) <= X"00";
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if(op_start = '1') then
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wait for 20 ns;
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if(endfile(chkfile)) then -- end of simulation
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plaintext(0,0) <= X"01";
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file_close(chkfile);
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wait for 20 ns;
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plaintext(0,0) <= X"02";
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wait for 40 ns;
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plaintext(0,0) <= X"03";
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wait;
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wait;
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end if;
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succeded := true;
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readline(chkfile, line_in); -- read in one expected result
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for i in 3 downto 0 loop
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for j in 3 downto 0 loop
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hread(line_in, exp_cipher_byte); -- read in one byte
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if(exp_cipher_byte /= cipher(3-j,3-i)) then
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succeded := false; -- check failed
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end if;
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end loop;
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end loop;
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-- writing the output line
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for i in 3 downto 0 loop
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for j in 3 downto 0 loop
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hwrite(line_out_file, cipher(3-j,3-i));
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hwrite(line_out, cipher(3-j,3-i));
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end loop;
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end loop;
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write(line_out_file, ' ');
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write(line_out, ' ');
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-- writing the comparison result
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write(line_out_file, succeded);
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write(line_out, succeded);
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writeline(opfile, line_out_file);
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writeline(OUTPUT, line_out);
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end if;
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wait for clk_period;
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end process;
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end process;
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end rtl;
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end rtl;
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No newline at end of file
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No newline at end of file
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