| Line 42... |
Line 42... |
---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Project: AESFast
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-- Author: Subhasis
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Last Modified: 25/03/10
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-- Email: subhasis256@gmail.com
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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------------------------------------------------------
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--
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--
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-- Description: The AddKey step
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-- Description: The AddKey step
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-- Ports:
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-- Ports:
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| Line 71... |
Line 71... |
use work.aes_pkg.all;
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use work.aes_pkg.all;
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entity addkey is
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entity addkey is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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roundkey: in datablock;
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roundkey: in datablock;
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datain: in datablock;
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datain: in datablock;
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rcon: in std_logic_vector(7 downto 0);
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rcon: in std_logic_vector(7 downto 0);
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dataout: out datablock;
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dataout: out datablock;
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fc3: out blockcol;
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fc3: out blockcol;
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| Line 87... |
Line 88... |
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architecture rtl of addkey is
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architecture rtl of addkey is
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component keysched1 is
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component keysched1 is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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roundkey: in datablock;
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roundkey: in datablock;
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rcon: in std_logic_vector(7 downto 0);
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rcon: in std_logic_vector(7 downto 0);
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fc3: out blockcol;
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fc3: out blockcol;
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c0: out blockcol;
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c0: out blockcol;
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c1: out blockcol;
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c1: out blockcol;
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| Line 100... |
Line 102... |
end component;
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end component;
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signal added: datablock;
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signal added: datablock;
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begin
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begin
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step1: keysched1 port map(
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step1: keysched1 port map(
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clk => clk,
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clk => clk,
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rst => rst,
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roundkey => roundkey,
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roundkey => roundkey,
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rcon => rcon,
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rcon => rcon,
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fc3 => fc3,
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fc3 => fc3,
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c0 => c0,
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c0 => c0,
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c1 => c1,
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c1 => c1,
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| Line 114... |
Line 117... |
g1: for j in 3 downto 0 generate
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g1: for j in 3 downto 0 generate
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added(i,j) <= datain(i,j) xor roundkey(i,j);
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added(i,j) <= datain(i,j) xor roundkey(i,j);
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end generate;
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end generate;
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end generate;
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end generate;
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process(clk)
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process(clk,rst)
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begin
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begin
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if(rising_edge(clk)) then
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if(rst = '1') then
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dataout <= zero_data;
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elsif(rising_edge(clk)) then
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dataout <= added;
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dataout <= added;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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