| Line 42... |
Line 42... |
---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Project: AESFast
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-- Author: Subhasis
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Last Modified: 25/03/10
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-- Email: subhasis256@gmail.com
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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------------------------------------------------------
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--
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--
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-- Description: The MixColumns step
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-- Description: The MixColumns step
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-- Ports:
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-- Ports:
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| Line 67... |
Line 67... |
use work.aes_pkg.all;
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use work.aes_pkg.all;
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entity colmix is
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entity colmix is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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datain: in datablock;
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datain: in datablock;
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inrkey: in datablock;
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inrkey: in datablock;
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outrkey: out datablock;
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outrkey: out datablock;
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dataout: out datablock
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dataout: out datablock
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);
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);
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| Line 78... |
Line 79... |
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architecture rtl of colmix is
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architecture rtl of colmix is
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component mixcol is
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component mixcol is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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in0: in std_logic_vector(7 downto 0);
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in0: in std_logic_vector(7 downto 0);
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in1: in std_logic_vector(7 downto 0);
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in1: in std_logic_vector(7 downto 0);
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in2: in std_logic_vector(7 downto 0);
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in2: in std_logic_vector(7 downto 0);
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in3: in std_logic_vector(7 downto 0);
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in3: in std_logic_vector(7 downto 0);
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out0: out std_logic_vector(7 downto 0);
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out0: out std_logic_vector(7 downto 0);
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| Line 94... |
Line 96... |
begin
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begin
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-- Do the mixcol operation on all the 4 columns
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-- Do the mixcol operation on all the 4 columns
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g0: for i in 3 downto 0 generate
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g0: for i in 3 downto 0 generate
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mix: mixcol port map(
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mix: mixcol port map(
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clk => clk,
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clk => clk,
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rst => rst,
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in0 => datain(0, i),
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in0 => datain(0, i),
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in1 => datain(1, i),
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in1 => datain(1, i),
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in2 => datain(2, i),
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in2 => datain(2, i),
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in3 => datain(3, i),
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in3 => datain(3, i),
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out0 => dataout(0, i),
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out0 => dataout(0, i),
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out1 => dataout(1, i),
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out1 => dataout(1, i),
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out2 => dataout(2, i),
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out2 => dataout(2, i),
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out3 => dataout(3, i)
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out3 => dataout(3, i)
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);
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);
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end generate;
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end generate;
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process(clk)
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process(clk,rst)
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begin
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begin
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if(rising_edge(clk)) then
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if(rst = '1') then
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outrkey <= zero_data;
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elsif(rising_edge(clk)) then
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outrkey <= inrkey;
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outrkey <= inrkey;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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No newline at end of file
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No newline at end of file
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