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----------------------------------------------------------------------
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---- ----
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---- Pipelined Aes IP Core ----
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---- ----
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---- This file is part of the Pipelined AES project ----
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---- http://www.opencores.org/cores/aes_pipe/ ----
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---- ----
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---- Description ----
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---- Implementation of AES IP core according to ----
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---- FIPS PUB 197 specification document. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author: ----
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---- - Subhasis Das, subhasis256@gmail.com ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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--
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-- Description: The MixColumns step
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-- Ports:
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-- clk: System Clock
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-- datain: Input State block
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-- inrkey: Input round key for passing on
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-- to the next stage, i.e. Addkey
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-- outrkey: Output round key to next stage
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-- dataout: Output state block
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------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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library work;
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use work.aes_pkg.all;
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entity colmix is
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port(
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clk: in std_logic;
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datain: in datablock;
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inrkey: in datablock;
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outrkey: out datablock;
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dataout: out datablock
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);
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end colmix;
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architecture rtl of colmix is
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component mixcol is
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port(
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clk: in std_logic;
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in0: in std_logic_vector(7 downto 0);
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in1: in std_logic_vector(7 downto 0);
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in2: in std_logic_vector(7 downto 0);
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in3: in std_logic_vector(7 downto 0);
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out0: out std_logic_vector(7 downto 0);
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out1: out std_logic_vector(7 downto 0);
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out2: out std_logic_vector(7 downto 0);
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out3: out std_logic_vector(7 downto 0)
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);
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end component;
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begin
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-- Do the mixcol operation on all the 4 columns
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g0: for i in 3 downto 0 generate
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mix: mixcol port map(
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clk => clk,
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in0 => datain(0, i),
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in1 => datain(1, i),
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in2 => datain(2, i),
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in3 => datain(3, i),
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out0 => dataout(0, i),
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out1 => dataout(1, i),
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out2 => dataout(2, i),
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out3 => dataout(3, i)
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);
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end generate;
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process(clk)
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begin
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if(rising_edge(clk)) then
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outrkey <= inrkey;
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end if;
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end process;
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end rtl;
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