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----------------------------------------------------------------------
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---- ----
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---- Pipelined Aes IP Core ----
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---- ----
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---- This file is part of the Pipelined AES project ----
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---- http://www.opencores.org/cores/aes_pipe/ ----
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---- ----
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---- Description ----
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---- Implementation of AES IP core according to ----
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---- FIPS PUB 197 specification document. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author: ----
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---- - Subhasis Das, subhasis256@gmail.com ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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--
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-- Description: First stage of key expansion
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-- Ports:
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-- clk: System Clock
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-- roundkey: Current roundkey
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-- rcon: Rcon byte for the next byte
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-- fc3: Sbox(RotWord(column3 of rkey)) xor Rcon
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-- c0: column0 of rkey
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-- c1: column0 xor column1
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-- c2: column0 xor column1 xor column2
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-- c3: column0 xor column1 xor column2 xor column3
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------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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library work;
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use work.aes_pkg.all;
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entity keysched1 is
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port(
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clk: in std_logic;
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roundkey: in datablock;
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rcon: in std_logic_vector(7 downto 0);
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fc3: out blockcol;
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c0: out blockcol;
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c1: out blockcol;
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c2: out blockcol;
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c3: out blockcol
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);
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end keysched1;
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architecture rtl of keysched1 is
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signal subst: blockcol;
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signal key0, key1, key2, key3: std_logic_vector(7 downto 0);
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component sbox is
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port(
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clk: in std_logic;
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bytein: in std_logic_vector(7 downto 0);
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byteout: out std_logic_vector(7 downto 0)
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);
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end component;
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signal rcon_d: std_logic_vector(7 downto 0);
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begin
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sub0: sbox port map(
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clk => clk,
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bytein => roundkey(0, 3),
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byteout => subst(3)
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);
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sub1: sbox port map(
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clk => clk,
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bytein => roundkey(1, 3),
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byteout => subst(0)
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);
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sub2: sbox port map(
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clk => clk,
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bytein => roundkey(2, 3),
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byteout => subst(1)
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);
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sub3: sbox port map(
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clk => clk,
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bytein => roundkey(3, 3),
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byteout => subst(2)
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);
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fc3(0) <= subst(0) xor rcon_d;
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fc3(1) <= subst(1);
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fc3(2) <= subst(2);
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fc3(3) <= subst(3);
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process(clk)
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begin
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if(rising_edge(clk)) then
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rcon_d <= rcon;
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for j in 3 downto 0 loop
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c0(j) <= roundkey(j, 0);
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c1(j) <= roundkey(j, 0) xor roundkey(j, 1);
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c2(j) <= roundkey(j, 0) xor roundkey(j, 1) xor roundkey(j, 2);
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c3(j) <= roundkey(j, 0) xor roundkey(j, 1) xor roundkey(j, 2) xor roundkey(j, 3);
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end loop;
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end if;
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end process;
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end rtl;
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