| Line 42... |
Line 42... |
---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Project: AESFast
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-- Author: Subhasis
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Last Modified: 25/03/10
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-- Email: subhasis256@gmail.com
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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------------------------------------------------------
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--
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--
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-- Description: First stage of key expansion
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-- Description: First stage of key expansion
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-- Ports:
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-- Ports:
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| Line 69... |
Line 69... |
use work.aes_pkg.all;
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use work.aes_pkg.all;
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|
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entity keysched1 is
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entity keysched1 is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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roundkey: in datablock;
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roundkey: in datablock;
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rcon: in std_logic_vector(7 downto 0);
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rcon: in std_logic_vector(7 downto 0);
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fc3: out blockcol;
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fc3: out blockcol;
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c0: out blockcol;
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c0: out blockcol;
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c1: out blockcol;
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c1: out blockcol;
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| Line 85... |
Line 86... |
signal subst: blockcol;
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signal subst: blockcol;
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signal key0, key1, key2, key3: std_logic_vector(7 downto 0);
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signal key0, key1, key2, key3: std_logic_vector(7 downto 0);
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component sbox is
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component sbox is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
|
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rst: in std_logic;
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bytein: in std_logic_vector(7 downto 0);
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bytein: in std_logic_vector(7 downto 0);
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byteout: out std_logic_vector(7 downto 0)
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byteout: out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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signal rcon_d: std_logic_vector(7 downto 0);
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signal rcon_d: std_logic_vector(7 downto 0);
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begin
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begin
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sub0: sbox port map(
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sub0: sbox port map(
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clk => clk,
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clk => clk,
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rst => rst,
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bytein => roundkey(0, 3),
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bytein => roundkey(0, 3),
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byteout => subst(3)
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byteout => subst(3)
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);
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);
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sub1: sbox port map(
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sub1: sbox port map(
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clk => clk,
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clk => clk,
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rst => rst,
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bytein => roundkey(1, 3),
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bytein => roundkey(1, 3),
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byteout => subst(0)
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byteout => subst(0)
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);
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);
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sub2: sbox port map(
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sub2: sbox port map(
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clk => clk,
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clk => clk,
|
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rst => rst,
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bytein => roundkey(2, 3),
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bytein => roundkey(2, 3),
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byteout => subst(1)
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byteout => subst(1)
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);
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);
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sub3: sbox port map(
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sub3: sbox port map(
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clk => clk,
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clk => clk,
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rst => rst,
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bytein => roundkey(3, 3),
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bytein => roundkey(3, 3),
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byteout => subst(2)
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byteout => subst(2)
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);
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);
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fc3(0) <= subst(0) xor rcon_d;
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fc3(0) <= subst(0) xor rcon_d;
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fc3(1) <= subst(1);
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fc3(1) <= subst(1);
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fc3(2) <= subst(2);
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fc3(2) <= subst(2);
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fc3(3) <= subst(3);
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fc3(3) <= subst(3);
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process(clk)
|
process(clk,rst)
|
begin
|
begin
|
if(rising_edge(clk)) then
|
if(rst = '1') then
|
|
rcon_d <= X"00";
|
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c0 <= zero_col;
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c1 <= zero_col;
|
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c2 <= zero_col;
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c3 <= zero_col;
|
|
elsif(rising_edge(clk)) then
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rcon_d <= rcon;
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rcon_d <= rcon;
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for j in 3 downto 0 loop
|
for j in 3 downto 0 loop
|
c0(j) <= roundkey(j, 0);
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c0(j) <= roundkey(j, 0);
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c1(j) <= roundkey(j, 0) xor roundkey(j, 1);
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c1(j) <= roundkey(j, 0) xor roundkey(j, 1);
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c2(j) <= roundkey(j, 0) xor roundkey(j, 1) xor roundkey(j, 2);
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c2(j) <= roundkey(j, 0) xor roundkey(j, 1) xor roundkey(j, 2);
|
