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----------------------------------------------------------------------
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---- ----
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---- Pipelined Aes IP Core ----
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---- ----
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---- This file is part of the Pipelined AES project ----
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---- http://www.opencores.org/cores/aes_pipe/ ----
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---- ----
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---- Description ----
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---- Implementation of AES IP core according to ----
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---- FIPS PUB 197 specification document. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author: ----
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---- - Subhasis Das, subhasis256@gmail.com ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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--
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-- Description: The MixColumns operation
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-- Ports:
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-- clk: System Clock
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-- in0: Byte 0 of a column
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-- in1: Byte 1 of a column
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-- in2: Byte 2 of a column
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-- in3: Byte 3 of a column
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-- out0: Byte 0 of output column
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-- out1: Byte 1 of output column
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-- out2: Byte 2 of output column
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-- out3: Byte 3 of output column
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-- keyblock: Input Key Blocks three at a time
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-- ciphertext: Output Cipher Block
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------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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library work;
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use work.aes_pkg.all;
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entity mixcol is
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port(
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clk: in std_logic;
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in0: in std_logic_vector(7 downto 0);
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in1: in std_logic_vector(7 downto 0);
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in2: in std_logic_vector(7 downto 0);
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in3: in std_logic_vector(7 downto 0);
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out0: out std_logic_vector(7 downto 0);
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out1: out std_logic_vector(7 downto 0);
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out2: out std_logic_vector(7 downto 0);
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out3: out std_logic_vector(7 downto 0)
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);
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end mixcol;
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architecture rtl of mixcol is
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signal d0, d1, d2, d3: std_logic_vector(7 downto 0);
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signal t0, t1, t2, t3: std_logic_vector(7 downto 0);
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signal sh0, sh1, sh2, sh3: std_logic_vector(7 downto 0);
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signal xored: std_logic_vector(7 downto 0);
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begin
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sh0(0) <= '0';
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sh1(0) <= '0';
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sh2(0) <= '0';
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sh3(0) <= '0';
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-----------------------------------------------------
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-- In GF(2^8) 2*x = (x << 1) xor 0x1b if x(7) = '1'
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-- (x << 1) else
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-- This just left shifts each byte by 1.
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shift: for i in 7 downto 1 generate
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sh0(i) <= in0(i-1);
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sh1(i) <= in1(i-1);
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sh2(i) <= in2(i-1);
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sh3(i) <= in3(i-1);
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end generate;
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-- Conditional XOR'ing
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d0 <= sh0 xor X"1b" when in0(7) = '1' else
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sh0;
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d1 <= sh1 xor X"1b" when in1(7) = '1' else
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sh1;
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d2 <= sh2 xor X"1b" when in2(7) = '1' else
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sh2;
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d3 <= sh3 xor X"1b" when in3(7) = '1' else
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sh3;
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----------------------------------------------------
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-- 3*x = 2*x xor x
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----------------------------------------------------
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t0 <= d0 xor in0;
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t1 <= d1 xor in1;
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t2 <= d2 xor in2;
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t3 <= d3 xor in3;
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xored <= in0 xor in1 xor in2 xor in3;
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process(clk)
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begin
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if(rising_edge(clk)) then
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out0 <= xored xor t0 xor d1;
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out1 <= xored xor t1 xor d2;
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out2 <= xored xor t2 xor d3;
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out3 <= xored xor t3 xor d0;
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end if;
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end process;
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end rtl;
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