| Line 42... |
Line 42... |
---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Project: AESFast
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-- Author: Subhasis
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Last Modified: 25/03/10
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-- Email: subhasis256@gmail.com
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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------------------------------------------------------
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--
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--
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-- Description: The MixColumns operation
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-- Description: The MixColumns operation
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-- Ports:
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-- Ports:
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| Line 72... |
Line 72... |
use work.aes_pkg.all;
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use work.aes_pkg.all;
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|
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entity mixcol is
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entity mixcol is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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in0: in std_logic_vector(7 downto 0);
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in0: in std_logic_vector(7 downto 0);
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in1: in std_logic_vector(7 downto 0);
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in1: in std_logic_vector(7 downto 0);
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in2: in std_logic_vector(7 downto 0);
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in2: in std_logic_vector(7 downto 0);
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in3: in std_logic_vector(7 downto 0);
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in3: in std_logic_vector(7 downto 0);
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out0: out std_logic_vector(7 downto 0);
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out0: out std_logic_vector(7 downto 0);
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| Line 123... |
Line 124... |
t1 <= d1 xor in1;
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t1 <= d1 xor in1;
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t2 <= d2 xor in2;
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t2 <= d2 xor in2;
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t3 <= d3 xor in3;
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t3 <= d3 xor in3;
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|
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xored <= in0 xor in1 xor in2 xor in3;
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xored <= in0 xor in1 xor in2 xor in3;
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process(clk)
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process(clk,rst)
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begin
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begin
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if(rising_edge(clk)) then
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if(rst = '1') then
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out0 <= X"00";
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out1 <= X"00";
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out2 <= X"00";
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out3 <= X"00";
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elsif(rising_edge(clk)) then
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out0 <= xored xor t0 xor d1;
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out0 <= xored xor t0 xor d1;
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out1 <= xored xor t1 xor d2;
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out1 <= xored xor t1 xor d2;
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out2 <= xored xor t2 xor d3;
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out2 <= xored xor t2 xor d3;
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out3 <= xored xor t3 xor d0;
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out3 <= xored xor t3 xor d0;
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end if;
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end if;
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