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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Revision 0.02 - Fixed NMI bug
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// Revision 0.02 - Fixed NMI bug
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// Revision 0.03 - Updated clocking constants to support higher frequencies
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`else
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`else
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module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
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module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
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parameter DELAY = 1; // delay in waves of baseclk
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parameter DELAY = 1; // delay in semi-waves of baseclk
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initial phi_1 = 0;
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initial phi_1 = 0;
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integer cnt = 0;
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integer cnt = 0;
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always @(posedge baseclk) begin
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always @(posedge baseclk) begin
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if (phi_0 != phi_1) begin
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if (phi_0 != phi_1) begin
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end
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end
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endmodule
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endmodule
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// baseclk is used to simulate delays on a real hardware
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// baseclk is used to simulate delays on a real hardware
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module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
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module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
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parameter DELAY1 = 3, DELAY2 = 1; // delays in waves of baseclk
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parameter DELAY1 = 2, DELAY2 = 0; // delays in semi-waves of baseclk
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wire phi_1_neg, phi_01;
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wire phi_1_neg, phi_01;
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ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
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ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
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assign phi_1 = ~phi_1_neg;
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assign phi_1 = ~phi_1_neg;
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