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// Company: BMSTU
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// Company: BMSTU
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// Engineer: Oleg Odintsov
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// Engineer: Oleg Odintsov
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//
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//
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// Create Date: 10:50:36 02/15/2012
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// Create Date: 10:50:36 02/15/2012
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// Design Name:
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// Design Name:
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// Module Name: ag_6502
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// Module Name: my6502
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// Project Name: Agat Hardware Project
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// Project Name: Agat Hardware Project
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Revision 0.02 - Fixed NMI bug
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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Line 38... |
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`else
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`else
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module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
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module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
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parameter DELAY = 1; // delay in semi-waves of baseclk
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parameter DELAY = 1; // delay in waves of baseclk
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initial phi_1 = 0;
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initial phi_1 = 0;
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integer cnt = 0;
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integer cnt = 0;
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always @(posedge baseclk) begin
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always @(posedge baseclk) begin
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if (phi_0 != phi_1) begin
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if (phi_0 != phi_1) begin
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if (!cnt) begin phi_1 <= ~phi_1; cnt <= DELAY; end
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if (!cnt) begin phi_1 <= phi_0; cnt <= DELAY; end
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else cnt <= cnt - 1;
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else cnt <= cnt - 1;
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end
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end
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end
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end
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endmodule
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endmodule
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// baseclk is used to simulate delays on a real hardware
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// baseclk is used to simulate delays on a real hardware
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module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
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module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
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parameter DELAY1 = 3, DELAY2 = 1; // delays in semi-waves of baseclk
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parameter DELAY1 = 3, DELAY2 = 1; // delays in waves of baseclk
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wire phi_1_neg, phi_01;
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wire phi_1_neg, phi_01;
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ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
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ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
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assign phi_1 = ~phi_1_neg;
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assign phi_1 = ~phi_1_neg;
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`endif
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`endif
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reg rdyg = 1;
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reg rdyg = 1;
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reg[2:0] T = 7;
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reg[2:0] T = 7;
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reg[7:0] IR ='h18;
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reg[7:0] IR ='h00;
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reg[15:0] PC = 0;
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reg[15:0] PC = 0;
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wire[7:0] PCH = PC[15:8], PCL = PC[7:0];
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wire[7:0] PCH = PC[15:8], PCL = PC[7:0];
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reg[7:0] EAL, EAH;
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reg[7:0] EAL, EAH;
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wire[15:0] EA = {EAH, EAL};
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wire[15:0] EA = {EAH, EAL};
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wire nmi_active = ~nmi & nmi_prev;
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wire nmi_active = ~nmi & nmi_prev;
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wire int_active = irq_active | nmi_active;
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wire int_active = irq_active | nmi_active;
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wire rst_active = ~rst;
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wire rst_active = ~rst;
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wire so_active = so & ~so_prev;
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wire so_active = so & ~so_prev;
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wire[7:0] IR_in = int_active?8'b0:db_in;
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wire[1:0] vec_bits=
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wire[1:0] vec_bits=
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nmi_active?2'b01:
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nmi_active?2'b01:
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rst_active?2'b10:
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rst_active?2'b10:
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2'b11;
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2'b11;
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wire[15:0] vec_addr = {{13{1'b1}}, vec_bits, 1'b0};
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wire[15:0] vec_addr = {{13{1'b1}}, vec_bits, 1'b0};
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wire[7:0] IR_eff = int_active?8'b0:IR;
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wire[10:0] L = {T, IR};
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wire[10:0] L = {T, IR_eff};
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`include "states.v"
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`include "states.v"
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assign read = ~A_RW_W;
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assign read = ~A_RW_W;
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assign sync = !T;
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assign sync = !T;
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E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
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E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
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E_T__0IF_C7F? CF_OUT == EAL[7]:
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E_T__0IF_C7F? CF_OUT == EAL[7]:
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E_T__0;
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E_T__0;
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always @(negedge phi_2) if (rdyg) begin
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always @(negedge phi_2) if (rdyg) begin
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if (E_PC__PC_1) PC <= PC + 1;
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if (E_PC__PC_1) begin
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else if (E_PC__EA) PC <= EA;
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if (T || (!int_active && !rst_active)) PC <= PC + 1;
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end else if (E_PC__EA) PC <= EA;
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else begin
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else begin
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if (E_PCH__RES) PC[15:8] <= RES;
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if (E_PCH__RES) PC[15:8] <= RES;
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if (E_PCL__ALU) PC[7:0] <= ALU;
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if (E_PCL__ALU) PC[7:0] <= ALU;
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else if (E_PCL__RES) PC[7:0] <= RES;
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else if (E_PCL__RES) PC[7:0] <= RES;
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else if (E_PCL__EAL) PC[7:0] <= EAL;
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else if (E_PCL__EAL) PC[7:0] <= EAL;
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else if (E_PCL__DB) PC[7:0] <= db_in;
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else if (E_PCL__DB) PC[7:0] <= db_in;
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end
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end
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if (!T) begin
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if (!T) begin
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IR <= db_in;
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IR <= IR_in;
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if (!db_in) begin // BRK instruction
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if (!IR_in) begin // BRK instruction
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{EAH, EAL} <= vec_addr;
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{EAH, EAL} <= vec_addr;
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end
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end
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nmi_prev <= nmi;
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nmi_prev <= nmi;
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end
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end
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Line 326... |
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eALU <= {CF_OUT, RES};
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eALU <= {CF_OUT, RES};
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if (cond) begin
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if (cond) begin
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T <= 0;
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T <= 0;
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if (!IR_eff) begin
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if (!IR) begin
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FLAG_B <= !IR;
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FLAG_B <= !int_active;
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FLAG_I <= 1;
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FLAG_I <= 1;
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end
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end
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end else T <= T + ((E_T__T_1IF_ALUCZ && !ALU_CF)?2: 1);
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end else T <= T + ((E_T__T_1IF_ALUCZ && !ALU_CF)?2: 1);
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if (rst_active) begin
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if (rst_active) begin
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