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[/] [ag_6502/] [trunk/] [agat7/] [ag_6502.v] - Diff between revs 6 and 7
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`else
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`else
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module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
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module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
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parameter DELAY = 1; // delay in semi-waves of baseclk
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parameter DELAY = 1; // delay in waves of baseclk
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initial phi_1 = 0;
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initial phi_1 = 0;
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integer cnt = 0;
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integer cnt = 0;
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always @(posedge baseclk) begin
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always @(posedge baseclk) begin
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if (phi_0 != phi_1) begin
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if (phi_0 != phi_1) begin
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