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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module ROM2kx8(input[10:0] adr, input cs, output[7:0] DO);
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module ROM2kx8(input CLK, input[10:0] AB, input CS, output[7:0] DO);
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reg[7:0] mem[0:2047];
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reg[7:0] mem[0:2047];
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assign DO = cs?mem[adr]:8'bZ;
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reg[7:0] R;
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assign DO = CS? R: 8'bZ;
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always @(posedge CLK) if (CS) R <= mem[AB];
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initial begin
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initial begin
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`include "monitor7.v"
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`include "monitor7.v"
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end
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end
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endmodule
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endmodule
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module ag_main(
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module ag_main(
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input clk50,
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input clk50x,
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input[3:0] btns,
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input[3:0] btns,
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input[3:0] switches,
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output[7:0] leds,
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output[7:0] leds,
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output[3:0] controls,
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output[3:0] controls,
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output[4:0] vga_bus,
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output[4:0] vga_bus,
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input[1:0] ps2_bus_in
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input[1:0] ps2_bus_in
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);
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);
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// assign leds = 0;
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// assign leds = 0;
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// assign controls = 0;
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// assign controls = 0;
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// assign vga_bus = 0;
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// assign vga_bus = 0;
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wire clk1, clk10;
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wire clk1, clk1x, clk10, clk50;
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reg turbo = 0;
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BUFG bg1(clk50, clk50x);
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clk_div#5 cd5(clk50, clk10);
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clk_div#5 cd5(clk50, clk10);
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clk_div#10 cd10(clk10, clk1);
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clk_div#10 cd10(clk10, clk1x);
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BUFGMUX bgm1(clk1, clk1x, clk10, turbo);
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// assign clk1 = turbo?clk10:clk1x;
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wire clk_vram;
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wire clk_vram;
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wire[13:0] AB2;
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wire[13:0] AB2;
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wire[15:0] DI2;
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wire[15:0] DI2;
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wire rom_cs, ram_cs;
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wire rom_cs, ram_cs;
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wire phi_1, phi_2;
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wire phi_1, phi_2;
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RAM32Kx8x16 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO,
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RAM32Kx8x16 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO,
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clk_vram, AB2, 1, DI2);
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clk_vram, AB2, 1, DI2);
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ROM2kx8 rom1(AB[10:0], rom_cs, DI);
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ROM2kx8 rom1(phi_2, AB[10:0], rom_cs, DI);
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wire [3:0] AB_HH = AB[15:12];
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wire [3:0] AB_HH = AB[15:12];
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wire [3:0] AB_HL = AB[11:8];
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wire [3:0] AB_HL = AB[11:8];
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wire [3:0] AB_LH = AB[7:4];
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wire [3:0] AB_LH = AB[7:4];
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wire [3:0] AB_LL = AB[3:0];
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wire [3:0] AB_LL = AB[3:0];
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wire AB_C00X = AB_C0XX && (AB_LH == 4'h0);
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wire AB_C00X = AB_C0XX && (AB_LH == 4'h0);
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wire AB_C01X = AB_C0XX && (AB_LH == 4'h1);
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wire AB_C01X = AB_C0XX && (AB_LH == 4'h1);
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wire AB_C02X = AB_C0XX && (AB_LH == 4'h2);
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wire AB_C02X = AB_C0XX && (AB_LH == 4'h2);
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wire AB_C03X = AB_C0XX && (AB_LH == 4'h3);
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wire AB_C03X = AB_C0XX && (AB_LH == 4'h3);
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wire AB_C04X = AB_C0XX && (AB_LH == 4'h4);
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wire AB_C05X = AB_C0XX && (AB_LH == 4'h5);
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wire AB_C7XX = AB_CXXX && (AB_HL == 4'h7);
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wire AB_C7XX = AB_CXXX && (AB_HL == 4'h7);
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reg timer_ints = 0;
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assign rom_cs = AB_FXXX && AB[11]; // F800-FFFF
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assign rom_cs = AB_FXXX && AB[11]; // F800-FFFF
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assign ram_cs = !AB[15];
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assign ram_cs = !AB[15];
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reg reset_auto = 1;
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reg reset_auto = 1;
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wire reset;
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wire reset;
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wire WE = ~read; // write enable
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wire WE = ~read; // write enable
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supply0 IRQ; // interrupt request
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supply0 IRQ; // interrupt request
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supply0 NMI; // non-maskable interrupt request
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wire NMI; // non-maskable interrupt request
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supply1 RDY; // Ready signal. Pauses CPU when RDY=0
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supply1 RDY; // Ready signal. Pauses CPU when RDY=0
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supply1 SO; // Set Overflow, not used.
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supply1 SO; // Set Overflow, not used.
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wire SYNC;
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wire SYNC;
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assign NMI = timer_ints & vga_bus[0];
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reg[7:0] vmode = 0;
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reg[7:0] vmode = 0;
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wire[7:0] key_reg;
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wire[7:0] key_reg;
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wire key_rus;
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wire key_rus;
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reg key_clear = 0;
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reg key_clear = 0;
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Line 127... |
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ag_keyb keyb(phi_2, ps2_bus, key_reg, key_clear, key_rus, key_rst, key_pause);
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ag_keyb keyb(phi_2, ps2_bus, key_reg, key_clear, key_rus, key_rst, key_pause);
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assign DI = (AB_C00X && !WE)?key_reg:8'bZ;
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assign DI = (AB_C00X && !WE)?key_reg:8'bZ;
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wire reset_all = reset | reset_auto | key_rst;
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always @(posedge phi_2) begin
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always @(posedge phi_2) begin
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turbo <= switches[0];
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key_clear <= AB_C01X;
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key_clear <= AB_C01X;
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if (AB_C04X) timer_ints <= 1;
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else if (AB_C05X || reset_all) timer_ints <= 0;
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if (AB_C02X) tape_out_reg <= ~tape_out_reg;
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if (AB_C02X) tape_out_reg <= ~tape_out_reg;
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if (AB_C03X) beep_reg <= ~beep_reg;
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if (AB_C03X) beep_reg <= ~beep_reg;
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if (AB_C7XX) vmode <= AB_L;
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if (AB_C7XX) vmode <= AB_L;
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end
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end
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always @(posedge vga_bus[0]) begin
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always @(posedge vga_bus[0]) begin
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reset_auto <= 0;
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reset_auto <= 0;
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end
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end
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ag6502_ext_clock clk(clk50, clk1, phi_1, phi_2);
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ag6502_ext_clock clk(clk50, clk1, phi_1, phi_2);
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ag6502 cpu(clk1, phi_1, phi_2, AB, read, DI, DO,
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ag6502 cpu(clk1, phi_1, phi_2, AB, read, DI, DO,
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RDY & ~key_pause, ~(reset | reset_auto | key_rst), ~IRQ, ~NMI, SO, SYNC);
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RDY & ~key_pause, ~reset_all, ~IRQ, ~NMI, SO, SYNC);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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