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https://opencores.org/ocsvn/ag_6502/ag_6502/trunk
[/] [ag_6502/] [trunk/] [digger/] [ag_main.v] - Diff between revs 5 and 8
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Rev 8 |
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Line 43... |
reg[7:0] R;
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reg[7:0] R;
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assign DO = CS? R: 8'bZ;
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assign DO = CS? R: 8'bZ;
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always @(posedge CLK) if (CS) if (READ) R <= mem[AB]; else mem[AB] <= DI;
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always @(posedge CLK) if (CS) if (READ) R <= mem[AB]; else mem[AB] <= DI;
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endmodule
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endmodule
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module ag_main(
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module ag_main(
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input clk50,
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input clk50x,
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input[4:0] btns,
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input[4:0] btns,
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input[3:0] switches,
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input[3:0] switches,
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output[7:0] leds,
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output[7:0] leds,
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output[3:0] controls,
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output[3:0] controls,
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output[4:0] vga_bus,
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output[4:0] vga_bus,
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input[1:0] ps2_bus_in,
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input[1:0] ps2_bus_in,
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output clk_cpu
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output clk_cpu
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);
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);
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wire clk1, clk1x, clk10;
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wire clk1, clk1x, clk10, clk50;
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reg turbo = 0;
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reg turbo = 0;
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BUFG bg1(clk50, clk50x);
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clk_div#5 cd5(clk50, clk10);
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clk_div#5 cd5(clk50, clk10);
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clk_div#10 cd10(clk10, clk1x);
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clk_div#10 cd10(clk10, clk1x);
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assign clk1 = turbo?clk10:clk1x;
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BUFGMUX bgm1(clk1, clk1x, clk10, turbo);
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// assign clk1 = turbo?clk10:clk1x;
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wire clk_vram;
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wire clk_vram;
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wire[13:0] AB2;
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wire[13:0] AB2;
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wire[15:0] DI2;
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wire[15:0] DI2;
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