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https://opencores.org/ocsvn/ahb_master/ahb_master/trunk
[/] [ahb_master/] [trunk/] [src/] [base/] [axi2ahb_ctrl.v] - Diff between revs 2 and 3
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| Rev 2 |
Rev 3 |
| Line 42... |
Line 42... |
wire ahb_last;
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wire ahb_last;
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wire data_last;
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wire data_last;
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reg [4:0] cmd_counter;
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reg [4:0] cmd_counter;
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reg rdata_phase;
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reg rdata_phase;
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reg wdata_phase;
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reg wdata_phase;
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wire data_phase;
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reg [1:0] HTRANS;
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reg [1:0] HTRANS;
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reg [2:0] HBURST;
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reg [2:0] HBURST;
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reg [1:0] HSIZE;
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reg [1:0] HSIZE;
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reg HWRITE;
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reg HWRITE;
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reg [ADDR_BITS-1:0] HADDR;
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reg [ADDR_BITS-1:0] HADDR;
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assign ahb_finish = ahb_ack_last;
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assign ahb_finish = ahb_ack_last;
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assign data_ready = cmd_read ? rdata_ready : wdata_ready;
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assign data_ready = cmd_read ? rdata_ready : wdata_ready;
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assign data_phase = wdata_phase | rdata_phase;
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assign ahb_idle = HTRANS == TRANS_IDLE;
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assign ahb_idle = HTRANS == TRANS_IDLE;
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assign ahb_ack = HTRANS[1] & HREADY;
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assign ahb_ack = HTRANS[1] & HREADY;
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assign ahb_ack_last = ahb_last & ahb_ack;
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assign ahb_ack_last = ahb_last & ahb_ack;
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assign ahb_start = (~cmd_empty) & data_ready & ahb_idle;
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assign ahb_start = (~cmd_empty) & data_ready & ahb_idle & (HREADY | (~data_phase));
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assign data_last = HREADY & (ahb_idle || (HTRANS == TRANS_NONSEQ));
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assign data_last = HREADY & (ahb_idle || (HTRANS == TRANS_NONSEQ));
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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cmd_counter <= #FFD 4'd0;
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cmd_counter <= #FFD 4'd0;
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