URL https://opencores.org/ocsvn/ahb_master/ahb_master/trunk

Subversion Repositories ahb_master

[/] [ahb_master/] [trunk/] [src/] [base/] [def_ic_static.txt] - Diff between revs 11 and 13

Rev 11	Rev 13
Line 25...	Line 25...
`//// PURPOSE. See the GNU Lesser General Public License for more////`	`//// PURPOSE. See the GNU Lesser General Public License for more////`
`//// details. http://www.gnu.org/licenses/lgpl.html ////`	`//// details. http://www.gnu.org/licenses/lgpl.html ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////##>`	`//////////////////////////////////////////////////////////////////##>`

	`VERIFY (DATA_BITS in 32, 64) ##stub supports 32 or 64 bits data bus`
	`VERIFY (SIZE_BITS in 2, 3) ##stub supports 32 or 64 bits data bus`


`SWAP.GLOBAL MODEL_NAME AXI interconnect fabric`	`SWAP.GLOBAL MODEL_NAME AXI interconnect fabric`

`SWAP MSTRS MASTER_NUM`	`SWAP MSTRS MASTER_NUM`
`SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))`	`SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))`

Line 50...	Line 54...

`GROUP IC_AXI_A is {`	`GROUP IC_AXI_A is {`
`ID ID_BITS input SON(CHANGE 1)`	`ID ID_BITS input SON(CHANGE 1)`
`ADDR ADDR_BITS input`	`ADDR ADDR_BITS input`
`LEN 4 input`	`LEN 4 input`
`SIZE 2 input`	`SIZE SIZE_BITS input`
`BURST 2 input`	`BURST 2 input`
`CACHE 4 input`	`CACHE 4 input`
`PROT 3 input`	`PROT 3 input`
`LOCK 2 input`	`LOCK 2 input`
`USER USER_BITS input`	`USER USER_BITS input`