URL https://opencores.org/ocsvn/ahb_master/ahb_master/trunk

Subversion Repositories ahb_master

[/] [ahb_master/] [trunk/] [src/] [base/] [ic_dec.v] - Diff between revs 2 and 10

Rev 2	Rev 10
Line 30...	Line 30...
`OUTFILE PREFIX_ic_dec.v`	`OUTFILE PREFIX_ic_dec.v`

`ITER MX`	`ITER MX`
`ITER SX`	`ITER SX`

`LOOP MX`
`ITER MMX_IDX`
`ENDLOOP MX`

`module PREFIX_ic_dec (PORTS);`	`module PREFIX_ic_dec (PORTS);`

`input [ADDR_BITS-1:0] MMX_AADDR;`	`input [ADDR_BITS-1:0] MMX_AADDR;`
`input [ID_BITS-1:0] MMX_AID;`	`input [ID_BITS-1:0] MMX_AID;`
`output [SLV_BITS-1:0] MMX_ASLV;`	`output [SLV_BITS-1:0] MMX_ASLV;`
Line 50...	Line 46...
`reg MMX_AIDOK;`	`reg MMX_AIDOK;`

`LOOP MX`	`LOOP MX`
`always @(MMX_AADDR or MMX_AIDOK)`	`always @(MMX_AADDR or MMX_AIDOK)`
`begin`	`begin`
	`IFDEF TRUE(SLAVE_NUM==1)`
	`case (MMX_AIDOK)`
	`1'b1 : MMX_ASLV = SLV_BITS'd0;`
	`ELSE TRUE(SLAVE_NUM==1)`
`case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]})`	`case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]})`
`{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = 'dSX;`	`{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = SLV_BITS'dSX;`
`default : MMX_ASLV = 'dSERR;`	`ENDIF TRUE(SLAVE_NUM==1)`
	`default : MMX_ASLV = SLV_BITS'dSERR;`
`endcase`	`endcase`
`end`	`end`

`always @(MMX_AID)`	`always @(MMX_AID)`
`begin`	`begin`
`case (MMX_AID)`	`case (MMX_AID)`
`ID_MMX_IDMMX_IDX : MMX_AIDOK = 1'b1;`	`ID_BITS'GROUP_MMX_ID : MMX_AIDOK = 1'b1;`
`default : MMX_AIDOK = 1'b0;`	`default : MMX_AIDOK = 1'b0;`
`endcase`	`endcase`
`end`	`end`

`ENDLOOP MX`	`ENDLOOP MX`