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https://opencores.org/ocsvn/all_digital_fm_receiver/all_digital_fm_receiver/trunk
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LIBRARY ieee;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.ALL;
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entity FIR is
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port(
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clock : in std_logic;
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reset : in std_logic;
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data_in : in signed(11 downto 0);
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data_out : out std_logic_vector(11 downto 0)
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);
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end FIR;
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architecture behavior of FIR is
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signal d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15 : signed(15 downto 0);
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signal sum : signed(15 downto 0);
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begin
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process(clock,reset)
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begin
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if (reset = '1') then
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d0 <= (others => '0');
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d1 <= (others => '0');
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d2 <= (others => '0');
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d3 <= (others => '0');
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d4 <= (others => '0');
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d5 <= (others => '0');
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d6 <= (others => '0');
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d7 <= (others => '0');
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d8 <= (others => '0');
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d9 <= (others => '0');
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d10 <= (others => '0');
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d11 <= (others => '0');
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d12 <= (others => '0');
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d13 <= (others => '0');
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d14 <= (others => '0');
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d15 <= (others => '0');
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sum <= (others => '0');
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data_out <= (others => '0');
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ELSIF rising_edge(clock) THEN
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d0 <= data_in(11)&data_in(11)&data_in(11)&data_in(11)&data_in;
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d1 <= d0;
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d2 <= d1;
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d3 <= d2;
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d4 <= d3;
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d5 <= d4;
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d6 <= d5;
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d7 <= d6;
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d8 <= d7;
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d9 <= d8;
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d10 <= d9;
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d11 <= d10;
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d12 <= d11;
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d13 <= d12;
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d14 <= d13;
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d15 <= d14;
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sum <= (d0+d1+d2+d3+d4+d5+d6+d7+d8+d9+d10+d11+d12+d13+d14+d15) srl 4;
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data_out <= std_logic_vector(sum(11 downto 0));
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end if;
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end process;
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end behavior;
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