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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE IEEE.numeric_std.ALL;
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ENTITY multiplier IS
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-- Declarations
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port (CLK : in std_logic;
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RESET : in std_logic;
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input1 : in std_logic_vector(7 downto 0);
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input2 : in signed(7 downto 0);
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output : out signed(7 downto 0)
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);
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END multiplier ;
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ARCHITECTURE behavior OF multiplier IS
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signal out_temp : signed(15 downto 0);
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signal input1_buf : signed(15 downto 0);
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signal part0, part1, part2, part3, part4, part5, part6, part7 : signed(15 downto 0);
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begin
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process(CLK, RESET)
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begin
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if (RESET='1') then
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out_temp <= (others => '0');
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output <= (others => '0');
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input1_buf <= (others => '0');
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part0 <= (others => '0');
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part1 <= (others => '0');
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part2 <= (others => '0');
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part3 <= (others => '0');
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part4 <= (others => '0');
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part5 <= (others => '0');
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part6 <= (others => '0');
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part7 <= (others => '0');
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elsif rising_edge(CLK) then
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input1_buf <= input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&signed(input1);
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if (input2(0)='1') then
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part0 <= -(input1_buf);
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else
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part0 <= (others => '0');
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end if;
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if (input2(1)='1') then
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if (input2(0)='1') then
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part1 <= (others => '0');
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else
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part1 <= -(input1_buf);
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end if;
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else
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if (input2(0)='1') then
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part1 <= input1_buf;
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else
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part1 <= (others => '0');
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end if;
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end if;
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if (input2(2)='1') then
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if (input2(1)='1') then
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part2 <= (others => '0');
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else
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part2 <= -(input1_buf);
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end if;
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else
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if (input2(1)='1') then
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part2 <= input1_buf;
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else
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part2 <= (others => '0');
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end if;
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end if;
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if (input2(3)='1') then
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if (input2(2)='1') then
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part3 <= (others => '0');
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else
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part3 <= -(input1_buf);
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end if;
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else
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if (input2(2)='1') then
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part3 <= input1_buf;
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else
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part3 <= (others => '0');
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end if;
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end if;
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if (input2(4)='1') then
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if (input2(3)='1') then
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part4 <= (others => '0');
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else
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part4 <= -(input1_buf);
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end if;
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else
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if (input2(3)='1') then
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part4 <= input1_buf;
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else
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part4 <= (others => '0');
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end if;
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end if;
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if (input2(5)='1') then
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if (input2(4)='1') then
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part5 <= (others => '0');
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else
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part5 <= -(input1_buf);
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end if;
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else
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if (input2(4)='1') then
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part5 <= input1_buf;
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else
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part5 <= (others => '0');
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end if;
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end if;
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if (input2(6)='1') then
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if (input2(5)='1') then
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part6 <= (others => '0');
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else
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part6 <= -(input1_buf);
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end if;
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else
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if (input2(5)='1') then
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part6 <= input1_buf;
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else
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part6 <= (others => '0');
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end if;
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end if;
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if (input2(7)='1') then
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if (input2(6)='1') then
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part7 <= (others => '0');
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else
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part7 <= -(input1_buf);
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end if;
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else
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if (input2(6)='1') then
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part7 <= input1_buf;
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else
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part7 <= (others => '0');
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end if;
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end if;
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out_temp <= part0+(part1(14 downto 0)&'0')+(part2(13 downto 0)&"00")+(part3(12 downto 0)&"000")+(part4(11 downto 0)&"0000")+(part5(10 downto 0)&"00000")+(part6(9 downto 0)&"000000")+(part7(8 downto 0)&"0000000");
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output <= out_temp(15 downto 8);
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end if;
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end process;
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END behavior;
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