| Line 32... |
Line 32... |
module TopLevel(
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module TopLevel(
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CLK_50MHZ_IN, MASTER_RST,
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CLK_50MHZ_IN, MASTER_RST,
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H_SYNC, V_SYNC, VGA_OUTPUT,
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H_SYNC, V_SYNC, VGA_OUTPUT,
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PS2C, PS2D,
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PS2C, PS2D,
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// TIME_BASE,
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// TIME_BASE,
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ADC_DATA, ADC_CLK,
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ADC_DATA, CLK_ADC,
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VGA_RAM_ADDR, VGA_RAM_DATA,
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VGA_RAM_ADDR, VGA_RAM_DATA,
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VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
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VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
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|
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SEG_OUT, SEG_SEL, leds, SHOW_LEVELS_BUTTON
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SEG_OUT, SEG_SEL, leds, SHOW_LEVELS_BUTTON
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);
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);
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| Line 55... |
Line 55... |
input CLK_50MHZ_IN, MASTER_RST;
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input CLK_50MHZ_IN, MASTER_RST;
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output H_SYNC, V_SYNC;
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output H_SYNC, V_SYNC;
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output[2:0] VGA_OUTPUT;
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output[2:0] VGA_OUTPUT;
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//input[5:0] TIME_BASE;
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//input[5:0] TIME_BASE;
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inout PS2C, PS2D;
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inout PS2C, PS2D;
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input[7:0] ADC_DATA;
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input[8:0] ADC_DATA;
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output ADC_CLK;
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output CLK_ADC;
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output[17:0] VGA_RAM_ADDR;
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output[17:0] VGA_RAM_ADDR;
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inout[15:0] VGA_RAM_DATA;
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inout[15:0] VGA_RAM_DATA;
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output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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|
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output[7:0] leds;
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output[7:0] leds;
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| Line 76... |
Line 76... |
wire CLK_50MHZ_IN, MASTER_RST;
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wire CLK_50MHZ_IN, MASTER_RST;
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wire H_SYNC, V_SYNC;
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wire H_SYNC, V_SYNC;
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wire[2:0] VGA_OUTPUT;
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wire[2:0] VGA_OUTPUT;
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wire[5:0] TIME_BASE;
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wire[5:0] TIME_BASE;
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wire PS2C, PS2D;
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wire PS2C, PS2D;
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wire[7:0] ADC_DATA;
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wire[8:0] ADC_DATA;
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wire ADC_CLK;
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wire CLK_ADC;
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wire[17:0] VGA_RAM_ADDR;
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wire[17:0] VGA_RAM_ADDR;
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wire[15:0] VGA_RAM_DATA;
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wire[15:0] VGA_RAM_DATA;
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wire VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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wire VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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| Line 92... |
Line 92... |
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//==================================================================//
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//==================================================================//
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// TEMP //
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// TEMP //
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//==================================================================//
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//==================================================================//
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reg[8:0] fake_adcData;
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wire[17:0] VGA_RAM_ADDRESS_w;
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wire[17:0] VGA_RAM_ADDRESS_w;
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wire[15:0] VGA_RAM_DATA_w;
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wire[15:0] VGA_RAM_DATA_w;
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wire L_BUTTON, R_BUTTON, M_BUTTON;
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wire L_BUTTON, R_BUTTON, M_BUTTON;
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|
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wire VGA_RAM_ACCESS_OK;
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wire VGA_RAM_ACCESS_OK;
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| Line 107... |
Line 109... |
wire[7:0] data_charRamRead;
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wire[7:0] data_charRamRead;
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reg[7:0] data_charRamRead_buf;
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reg[7:0] data_charRamRead_buf;
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wire[7:0] mask_charMap;
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wire[7:0] mask_charMap;
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reg[7:0] mask_charMap_buf;
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reg[7:0] mask_charMap_buf;
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wire[1:0] sm_trig;
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always @ (posedge CLK_50MHZ) begin
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always @ (posedge CLK_50MHZ) begin
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if(R_BUTTON) begin
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if(R_BUTTON) begin
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data_charRamRead_buf <= data_charRamRead_buf;
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data_charRamRead_buf <= data_charRamRead_buf;
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mask_charMap_buf <= mask_charMap_buf;
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mask_charMap_buf <= mask_charMap_buf;
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| Line 121... |
Line 122... |
end
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end
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end
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end
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sub_SegDriver segs(
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sub_SegDriver segs(
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.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST),
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.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST),
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.DATA_IN(data_charRamRead_buf),
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.DATA_IN(fake_adcData[7:0]),
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.SEG_OUT(SEG_OUT), .SEG_SEL(SEG_SEL)
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.SEG_OUT(SEG_OUT), .SEG_SEL(SEG_SEL)
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);
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);
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wire[7:0] leds;
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wire[7:0] leds;
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assign leds[1:0] = sm_trig;
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assign leds[7:0] = 8'b0;
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assign leds[7:2] = 6'b0;
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/*- - - - - - - - - - - - - */
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/*- - - - - - - - - - - - - */
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/* Fake ADC data */
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/* Fake ADC data */
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/*- - - - - - - - - - - - - */
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/*- - - - - - - - - - - - - */
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reg[7:0] fake_adcData;
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always @ (posedge CLK_ADC or posedge MASTER_RST) begin
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always @ (posedge CLK_VGA or posedge MASTER_RST) begin
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if(MASTER_RST)
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if(MASTER_RST)
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fake_adcData <= 8'd0;
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fake_adcData <= 9'd0;
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else
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else
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fake_adcData <= fake_adcData+1;
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fake_adcData <= fake_adcData+1;
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end
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end
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//==================================================================//
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//==================================================================//
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// SUBROUTINES //
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// SUBROUTINES //
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//==================================================================//
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//==================================================================//
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//d_DCM_VGA clock_gen_VGA (
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//d_DCM_VGA clock_gen_VGA (
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// .CLKIN_IN(CLK_50MHZ_IN),
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// .CLKIN_IN(CLK_50MHZ_IN),
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| Line 185... |
Line 185... |
.TRIGGER_LEVEL(TRIGGER_LEVEL)
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.TRIGGER_LEVEL(TRIGGER_LEVEL)
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);
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);
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wire[7:0] ADC_RAM_DATA;
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wire[8:0] ADC_RAM_DATA;
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wire[10:0] ADC_RAM_ADDR;
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wire[10:0] ADC_RAM_ADDR;
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wire ADC_RAM_CLK;
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wire ADC_RAM_CLK;
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wire[10:0] TRIG_ADDR;
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wire[10:0] TRIG_ADDR;
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wire VGA_WRITE_DONE;
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wire VGA_WRITE_DONE;
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ADCDataBuffer ram_ADC_databuffer(
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.CLK_64MHZ(CLK_64MHZ), .MASTER_RST(MASTER_RST),
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.CLK180_64MHZ(CLK180_64MHZ),
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.TIME_BASE(TIME_BASE),
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.RAM_ADDR(ADC_RAM_ADDR), .RAM_DATA(ADC_RAM_DATA), .RAM_CLK(ADC_RAM_CLK),
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// .ADC_DATA(ADC_DATA), .ADC_CLK(ADC_CLK),
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.ADC_DATA(fake_adcData), .ADC_CLK(ADC_CLK),
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.TRIG_ADDR(TRIG_ADDR), .VGA_WRITE_DONE(VGA_WRITE_DONE),
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.TRIGGER_LEVEL(TRIGGER_LEVEL[8:0]),
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.sm_trig(sm_trig)
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);
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ADCDataBuffer ADC_Data_Buffer(
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.CLK_64MHZ(CLK_64MHZ), .MASTER_CLK(MASTER_CLK), .MASTER_RST(MASTER_RST),
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.TIME_BASE(TIME_BASE), .TRIGGER_LEVEL(TRIGGER_LEVEL[8:0]), .ADC_DATA(ADC_DATA[7:0]),
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.CLK_ADC(CLK_ADC),
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.SNAP_DATA_EXT(ADC_RAM_DATA), .SNAP_ADDR_EXT(ADC_RAM_ADDR), .SNAP_CLK_EXT(ADC_RAM_CLK)
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);
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//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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// VGA //
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// VGA //
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//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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| Line 237... |
Line 232... |
.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST),
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.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST),
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.VGA_RAM_DATA(VGA_RAM_DATA_w), .VGA_RAM_ADDR(VGA_RAM_ADDRESS_w),
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.VGA_RAM_DATA(VGA_RAM_DATA_w), .VGA_RAM_ADDR(VGA_RAM_ADDRESS_w),
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.VGA_RAM_OE(VGA_RAM_OE_w), .VGA_RAM_WE(VGA_RAM_WE_w), .VGA_RAM_CS(VGA_RAM_CS_w),
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.VGA_RAM_OE(VGA_RAM_OE_w), .VGA_RAM_WE(VGA_RAM_WE_w), .VGA_RAM_CS(VGA_RAM_CS_w),
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.VGA_RAM_ACCESS_OK(VGA_RAM_ACCESS_OK),
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.VGA_RAM_ACCESS_OK(VGA_RAM_ACCESS_OK),
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.ADC_RAM_DATA(ADC_RAM_DATA), .ADC_RAM_ADDR(ADC_RAM_ADDR), .ADC_RAM_CLK(ADC_RAM_CLK),
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.ADC_RAM_DATA(ADC_RAM_DATA), .ADC_RAM_ADDR(ADC_RAM_ADDR), .ADC_RAM_CLK(ADC_RAM_CLK),
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.TIME_BASE(TIME_BASE),
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.TIME_BASE(TIME_BASE)
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.TRIG_ADDR(TRIG_ADDR), .VGA_WRITE_DONE(VGA_WRITE_DONE)
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);
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);
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Driver_VGA driver_VGA(
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Driver_VGA driver_VGA(
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.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST),
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.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST),
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.CLK_VGA(CLK_VGA),
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.CLK_VGA(CLK_VGA),
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