| Line 27... |
Line 27... |
// //
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// //
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//==================================================================//
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//==================================================================//
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|
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module ADCDataBuffer(
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module ADCDataBuffer(
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CLK_64MHZ, MASTER_CLK, MASTER_RST,
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CLK_64MHZ, MASTER_CLK, MASTER_RST,
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TIME_BASE, TRIGGER_LEVEL, ADC_DATA,
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TIMESCALE, TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET,
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ADC_DATA,
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CLK_ADC,
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CLK_ADC,
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SNAP_DATA_EXT, SNAP_ADDR_EXT, SNAP_CLK_EXT,
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SNAP_DATA_EXT, SNAP_ADDR_EXT, SNAP_CLK_EXT,
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sm_adc_ram, triggered
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TRIGGERSTYLE
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);
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);
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//==================================================================//
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//==================================================================//
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// PARAMETER DEFINITIONS //
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// PARAMETER DEFINITIONS //
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//==================================================================//
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//==================================================================//
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| Line 53... |
Line 54... |
// INPUTS / OUTPUTS //
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// INPUTS / OUTPUTS //
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//----------------------//
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//----------------------//
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input CLK_64MHZ;
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input CLK_64MHZ;
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input MASTER_CLK;
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input MASTER_CLK;
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input MASTER_RST;
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input MASTER_RST;
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input[5:0] TIME_BASE;
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input[3:0] TIMESCALE;
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input[8:0] TRIGGER_LEVEL;
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input[10:0] TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;
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input[8:0] ADC_DATA;
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input[8:0] ADC_DATA;
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|
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output CLK_ADC;
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output CLK_ADC;
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output[8:0] SNAP_DATA_EXT;
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output[8:0] SNAP_DATA_EXT;
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input[10:0] SNAP_ADDR_EXT;
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input[10:0] SNAP_ADDR_EXT;
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input SNAP_CLK_EXT;
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input SNAP_CLK_EXT;
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output[1:0]sm_adc_ram;
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input[1:0] TRIGGERSTYLE;
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output triggered;
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//----------------------//
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//----------------------//
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// WIRES / NODES //
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// WIRES / NODES //
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//----------------------//
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//----------------------//
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wire CLK_64MHZ, MASTER_CLK, MASTER_RST;
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wire CLK_64MHZ, MASTER_CLK, MASTER_RST;
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wire[5:0] TIME_BASE;
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wire[3:0] TIMESCALE;
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wire[8:0] TRIGGER_LEVEL;
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wire[10:0] TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;
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wire[8:0] ADC_DATA;
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wire[8:0] ADC_DATA;
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wire CLK_ADC;
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wire CLK_ADC;
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wire[8:0] SNAP_DATA_EXT;
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wire[8:0] SNAP_DATA_EXT;
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wire[10:0] SNAP_ADDR_EXT;
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wire[10:0] SNAP_ADDR_EXT;
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wire SNAP_CLK_EXT;
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wire SNAP_CLK_EXT;
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wire[1:0] TRIGGERSTYLE;
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|
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|
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//----------------------//
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//----------------------//
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// VARIABLES //
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// VARIABLES //
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//----------------------//
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//----------------------//
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| Line 102... |
Line 104... |
//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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|
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Driver_ADC ADC(
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Driver_ADC ADC(
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.CLK_64MHZ(CLK_64MHZ),
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.CLK_64MHZ(CLK_64MHZ),
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.MASTER_RST(MASTER_RST),
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.MASTER_RST(MASTER_RST),
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.TIME_BASE(TIME_BASE),
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.TIMESCALE(TIMESCALE),
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.CLK_ADC(CLK_ADC),
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.CLK_ADC(CLK_ADC),
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.ADC_DATA(ADC_DATA),
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.ADC_DATA(ADC_DATA),
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.DATA_OUT(data_from_adc)
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.DATA_OUT(data_from_adc)
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);
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);
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| Line 120... |
Line 122... |
//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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wire VCC, GND;
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wire VCC, GND;
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assign VCC = 1'b1;
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assign VCC = 1'b1;
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assign GND = 1'b0;
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assign GND = 1'b0;
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// move the following into a more organized area
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wire[10:0] vert_adjustment;
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assign vert_adjustment = (VERT_OFFSET);
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|
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RAMB16_S9_S9 ADC_QuasiFifo_Buffer(
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RAMB16_S9_S9 ADC_QuasiFifo_Buffer(
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.DOA(), .DOB(buf_adc_data[7:0]),
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.DOA(), .DOB(buf_adc_data[7:0]),
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.DOPA(), .DOPB(buf_adc_data[8]),
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.DOPA(), .DOPB(buf_adc_data[8]),
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.ADDRA(fifo_addr), .ADDRB(buf_adc_addr),
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.ADDRA(fifo_addr), .ADDRB(buf_adc_addr),
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.CLKA(CLK_ADC), .CLKB(CLK_ADC),
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.CLKA(CLK_ADC), .CLKB(CLK_ADC),
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| Line 137... |
Line 143... |
RAMB16_S9_S9 ADC_Data_Snapshot(
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RAMB16_S9_S9 ADC_Data_Snapshot(
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.DOA(), .DOB(SNAP_DATA_EXT[7:0]),
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.DOA(), .DOB(SNAP_DATA_EXT[7:0]),
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.DOPA(), .DOPB(SNAP_DATA_EXT[8]),
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.DOPA(), .DOPB(SNAP_DATA_EXT[8]),
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.ADDRA(snap_addr), .ADDRB(SNAP_ADDR_EXT),
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.ADDRA(snap_addr), .ADDRB(SNAP_ADDR_EXT),
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.CLKA(CLK_ADC), .CLKB(SNAP_CLK_EXT),
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.CLKA(CLK_ADC), .CLKB(SNAP_CLK_EXT),
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.DIA(buf_adc_data[7:0]), .DIB(8'b0),
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.DIA(buf_adc_data[7:0]+vert_adjustment[7:0]), .DIB(8'b0), /* VERTICAL OFFSET */
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.DIPA(buf_adc_data[8]), .DIPB(GND),
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.DIPA(buf_adc_data[8]+vert_adjustment[8]), .DIPB(GND), /* VERTICAL OFFSET */
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.ENA(VCC), .ENB(VCC),
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.ENA(VCC), .ENB(VCC),
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.WEA(VCC), .WEB(GND),
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.WEA(VCC), .WEB(GND),
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.SSRA(GND), .SSRB(GND)
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.SSRA(GND), .SSRB(GND)
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);
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);
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| Line 158... |
Line 164... |
else begin
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else begin
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// if(sm_adc_ram != ss_fifo_fill || sm_adc_ram != ss_fifo_half || sm_adc_ram != ss_save_snapshot)
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// if(sm_adc_ram != ss_fifo_fill || sm_adc_ram != ss_fifo_half || sm_adc_ram != ss_save_snapshot)
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// sm_adc_ram <= ss_fifo_fill;
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// sm_adc_ram <= ss_fifo_fill;
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if(sm_adc_ram == ss_fifo_fill && triggered)
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if(sm_adc_ram == ss_fifo_fill && triggered)
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sm_adc_ram <= ss_fifo_half;
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sm_adc_ram <= ss_fifo_half;
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else if(sm_adc_ram == ss_fifo_half && (fifo_addr == trig_addr + 11'd1024))
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else if(sm_adc_ram == ss_fifo_half && (fifo_addr == (trig_addr + 11'd1023)))
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sm_adc_ram <= ss_save_snapshot;
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sm_adc_ram <= ss_save_snapshot;
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else if(sm_adc_ram == ss_save_snapshot && snap_addr == 11'd2047)
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else if(sm_adc_ram == ss_save_snapshot && snap_addr == 11'd2047)
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sm_adc_ram <= ss_fifo_fill;
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sm_adc_ram <= ss_fifo_fill;
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else if(sm_adc_ram == ss_invalid)
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else if(sm_adc_ram == ss_invalid)
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sm_adc_ram <= ss_fifo_fill;
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sm_adc_ram <= ss_fifo_fill;
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| Line 191... |
Line 197... |
|
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always @ (posedge CLK_ADC or posedge MASTER_RST) begin
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always @ (posedge CLK_ADC or posedge MASTER_RST) begin
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if(MASTER_RST)
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if(MASTER_RST)
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triggered <= 1'b0;
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triggered <= 1'b0;
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else
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else
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triggered <= (data_from_adc_buffered < TRIGGER_LEVEL && data_from_adc >= TRIGGER_LEVEL);
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triggered <= (TRIGGERSTYLE == 2'b00) && (data_from_adc_buffered < TRIGGER_LEVEL && data_from_adc >= TRIGGER_LEVEL) || // >=
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(TRIGGERSTYLE == 2'b01) && (data_from_adc_buffered > TRIGGER_LEVEL && data_from_adc <= TRIGGER_LEVEL); // <=
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end
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end
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|
|
always @ (posedge triggered or posedge MASTER_RST) begin
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always @ (posedge triggered or posedge MASTER_RST) begin
|
if(MASTER_RST)
|
if(MASTER_RST)
|
trig_addr <= 11'b0;
|
trig_addr <= 11'b0;
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| Line 212... |
Line 219... |
buf_adc_addr <= 11'b0;
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buf_adc_addr <= 11'b0;
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end else if(sm_adc_ram == ss_save_snapshot) begin
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end else if(sm_adc_ram == ss_save_snapshot) begin
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snap_addr <= snap_addr + 1;
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snap_addr <= snap_addr + 1;
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buf_adc_addr <= buf_adc_addr + 1;
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buf_adc_addr <= buf_adc_addr + 1;
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end else begin
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end else begin
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buf_adc_addr <= trig_addr;
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buf_adc_addr <= trig_addr - (HORZ_OFFSET-11'd319); /* HORIZONTAL OFFSET */
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snap_addr <= 11'b0;
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snap_addr <= 11'b0;
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end
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end
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end
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end
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|
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endmodule
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endmodule
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