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[/] [alternascope/] [trunk/] [AdcDriver/] [d_Driver_RamBuffer.v] - Diff between revs 2 and 17

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Rev 2 Rev 17
Line 16... Line 16...
    TIME_BASE,
    TIME_BASE,
    RAM_ADDR, RAM_DATA, RAM_CLK,
    RAM_ADDR, RAM_DATA, RAM_CLK,
    ADC_DATA, ADC_CLK,
    ADC_DATA, ADC_CLK,
    TRIG_ADDR,
    TRIG_ADDR,
    VGA_WRITE_DONE,
    VGA_WRITE_DONE,
    TRIGGER_LEVEL
    TRIGGER_LEVEL,
 
    sm_trig
    );
    );
 
 
//==================================================================//
//==================================================================//
// PARAMETER DEFINITIONS                                            //
// PARAMETER DEFINITIONS                                            //
//==================================================================//
//==================================================================//
Line 51... Line 52...
output       ADC_CLK;
output       ADC_CLK;
output[10:0] TRIG_ADDR;
output[10:0] TRIG_ADDR;
input        VGA_WRITE_DONE;
input        VGA_WRITE_DONE;
input[8:0]   TRIGGER_LEVEL;
input[8:0]   TRIGGER_LEVEL;
 
 
 
output[1:0] sm_trig;
 
 
 
 
//----------------------//
//----------------------//
// WIRES / NODES        //
// WIRES / NODES        //
//----------------------//
//----------------------//
wire CLK_64MHZ, MASTER_RST, CLK180_64MHZ;
wire CLK_64MHZ, MASTER_RST, CLK180_64MHZ;
wire[5:0]  TIME_BASE;
wire[5:0]  TIME_BASE;
Line 74... Line 78...
 
 
 
 
//==================================================================//
//==================================================================//
// 'SUB-ROUTINES'                                                   //
// 'SUB-ROUTINES'                                                   //
//==================================================================//
//==================================================================//
 
 
//------------------------------------------------------------------//
//------------------------------------------------------------------//
// Instanstiate the ADC                                             //
// Instanstiate the ADC                                             //
//------------------------------------------------------------------//
//------------------------------------------------------------------//
wire[7:0] DATA_FROM_ADC;
wire[7:0] DATA_FROM_ADC;
Driver_ADC ADC(
Driver_ADC ADC(
Line 130... Line 133...
        sm_trig <= ss_wait_for_trig;
        sm_trig <= ss_wait_for_trig;
    else if(sm_trig == ss_wait_for_trig && trigger_detected == 1'b1)
    else if(sm_trig == ss_wait_for_trig && trigger_detected == 1'b1)
        sm_trig <= ss_fill_mem_half;
        sm_trig <= ss_fill_mem_half;
    else if(sm_trig == ss_fill_mem_half && mem_half_full == 1'b1)
    else if(sm_trig == ss_fill_mem_half && mem_half_full == 1'b1)
        sm_trig <= ss_write_buffer;
        sm_trig <= ss_write_buffer;
    else if(sm_trig == ss_write_buffer && trigger_detected == 1'b0 && VGA_WRITE_DONE == 1'b1)
    else if(sm_trig == ss_write_buffer && /*trigger_detected == 1'b0 &&*/ VGA_WRITE_DONE == 1'b1)
        sm_trig <= ss_wait_for_trig;
        sm_trig <= ss_wait_for_trig;
    else if(sm_trig == ss_invalid)
    else if(sm_trig == ss_invalid)
        sm_trig <= ss_wait_for_trig;
        sm_trig <= ss_wait_for_trig;
    else
    else
        sm_trig <= sm_trig;
        sm_trig <= sm_trig;
Line 148... Line 151...
        ADDRA <= 11'b0;
        ADDRA <= 11'b0;
    end else if(sm_trig == ss_wait_for_trig || sm_trig == ss_fill_mem_half)
    end else if(sm_trig == ss_wait_for_trig || sm_trig == ss_fill_mem_half)
        ADDRA <= ADDRA + 1;
        ADDRA <= ADDRA + 1;
    else
    else
        ADDRA <= ADDRA;
        ADDRA <= ADDRA;
 
//        ADDRA <= ADDRA + 1;
end
end
 
 
/* LATCHING THE TRIGGER  */
/* LATCHING THE TRIGGER  */
always @ (ADC_DATA) begin
always @ (ADC_DATA) begin
//    if(ADC_DATA >= P_trigger_level)
 
    if(ADC_DATA >= TRIGGER_LEVEL)
    if(ADC_DATA >= TRIGGER_LEVEL)
        trigger_detected = 1'b1;
        trigger_detected = 1'b1;
    else
    else
        trigger_detected = 1'b0;
        trigger_detected = 1'b0;
end
end
Line 166... Line 169...
    if(MASTER_RST == 1'b1)
    if(MASTER_RST == 1'b1)
        cnt_1024bytes <= 10'b0;
        cnt_1024bytes <= 10'b0;
    else if(sm_trig == ss_fill_mem_half)
    else if(sm_trig == ss_fill_mem_half)
        cnt_1024bytes <= cnt_1024bytes + 1;
        cnt_1024bytes <= cnt_1024bytes + 1;
    else
    else
        cnt_1024bytes <= cnt_1024bytes;
        cnt_1024bytes <= 10'b0;
 
//        cnt_1024bytes <= cnt_1024bytes;
end
end
 
 
always @ (cnt_1024bytes) begin
always @ (cnt_1024bytes) begin
    if(cnt_1024bytes == 10'h3FF)
    if(cnt_1024bytes == 10'h3FF)
        mem_half_full = 1'b1;
        mem_half_full = 1'b1;

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