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//==================================================================//
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//==================================================================//
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// File: d_VGAdriver.v //
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// File: d_VGAdriver.v //
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// Version: 0.0.0.2 //
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// Version: 0.0.0.3 //
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
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// Copyright (C) Stephen Pickett //
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// Copyright (C) Stephen Pickett //
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// Jun 09, 2005 //
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// Jun 09, 2005 //
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// //
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// //
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// This program is free software; you can redistribute it and/or //
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// This program is free software; you can redistribute it and/or //
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input[8:0] TRIGGER_LEVEL;
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input[8:0] TRIGGER_LEVEL;
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input SHOW_LEVELS;
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input SHOW_LEVELS;
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output[9:0] HCNT, VCNT;
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output[9:0] HCNT, VCNT;
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input[2:0] RGB_CHAR;
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input[2:0] RGB_CHAR;
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output[15:0] ram_vshift;
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//----------------------//
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//----------------------//
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// WIRES / NODES //
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// WIRES / NODES //
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//----------------------//
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//----------------------//
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// REGISTERS //
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// REGISTERS //
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//----------------------//
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//----------------------//
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//reg CLK_25MHZ; // General system clock for VGA timing
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wire CLK_25MHZ = CLK_VGA;
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wire CLK_25MHZ = CLK_VGA;
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reg [9:0] hcnt; // Counter - generates the H_SYNC signal
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reg [9:0] hcnt; // Counter - generates the H_SYNC signal
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reg [9:0] vcnt; // Counter - counts the H_SYNC pulses to generate V_SYNC signal
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reg [9:0] vcnt; // Counter - counts the H_SYNC pulses to generate V_SYNC signal
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reg[2:0] vga_out;
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reg[2:0] vga_out;
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// FUNCTIONAL DEFINITIONS //
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// FUNCTIONAL DEFINITIONS //
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//==================================================================//
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//==================================================================//
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assign HCNT = hcnt;
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assign HCNT = hcnt;
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assign VCNT = vcnt;
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assign VCNT = vcnt;
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//------------------------------------------------------------------//
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// CLOCK FUNCTIONS //
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//------------------------------------------------------------------//
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//always @ (posedge CLK_50MHZ or posedge MASTER_RST)
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// if (MASTER_RST == 1'b1)
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// CLK_25MHZ <= 1'b0;
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// else
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// CLK_25MHZ <= ~CLK_25MHZ;
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//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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// SYNC TIMING COUNTERS //
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// SYNC TIMING COUNTERS //
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//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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VGA_OUTPUT = P_yellow;
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VGA_OUTPUT = P_yellow;
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end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1) && hcnt >= 10'd556 && hcnt <= 10'd558) begin
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end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1) && hcnt >= 10'd556 && hcnt <= 10'd558) begin
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VGA_OUTPUT = P_yellow;
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VGA_OUTPUT = P_yellow;
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end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1) && hcnt == 10'd557) begin
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end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1) && hcnt == 10'd557) begin
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VGA_OUTPUT = P_yellow;
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VGA_OUTPUT = P_yellow;
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///*
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//------------------------------------------------------------------------------//
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//------------------------------------------------------------------------------//
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// MOVE THE WAVEFORM TO THE 'TOP' //
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// MOVE THE WAVEFORM TO THE 'TOP' //
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end else if(vga_out != 0) begin
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end else if(vga_out != 0) begin
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VGA_OUTPUT = vga_out;
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VGA_OUTPUT = vga_out;
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//*/
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//------------------------------------------------------------------------------//
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//------------------------------------------------------------------------------//
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// TOP, BOTTOM, LEFT AND RIGHT GRID LINES //
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// TOP, BOTTOM, LEFT AND RIGHT GRID LINES //
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end else if(vcnt == 10'd0 || vcnt == 10'd399 || vcnt == 10'd441) begin
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end else if(vcnt == 10'd0 || vcnt == 10'd399 || vcnt == 10'd441) begin
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VGA_OUTPUT = P_cyan;
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VGA_OUTPUT = P_cyan;
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end else if(hcnt == 10'd0 || hcnt == 10'd639) begin
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end else if(hcnt == 10'd0 || hcnt == 10'd639) begin
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// ...
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// ...
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// row 15: ram_addr = 24 and 25 for each pxl
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// row 15: ram_addr = 24 and 25 for each pxl
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// row 16: ram_addr = 23 and 25 for each pxl *
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// row 16: ram_addr = 23 and 25 for each pxl *
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// row 17: ram_addr = 23 and 25 for each pxl *
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// row 17: ram_addr = 23 and 25 for each pxl *
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// ...
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// ...
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/*reg[9:0] ram_hcnt;*/
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reg[4:0] ram_vcnt;
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reg[4:0] ram_vcnt;
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reg[15:0] ram_vshift;
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reg[15:0] ram_vshift;
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/*
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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if(MASTER_RST == 1'b1) begin
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ram_hcnt <= 10'd639;
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end else if(hcnt >= 10'd143 && hcnt <= 782) begin
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if(ram_hcnt == 10'd639)
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ram_hcnt <= 10'b0;
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else
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ram_hcnt <= ram_hcnt + 1'b1;
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end else begin
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ram_hcnt <= 10'd639;
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end
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end
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*/
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
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if(MASTER_RST == 1'b1) begin
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if(MASTER_RST == 1'b1) begin
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ram_vshift <= 16'h8000;
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ram_vshift <= 16'h8000;
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end else if(vcnt > 10'd399) begin
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end else if(vcnt > 10'd399) begin
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ram_vshift <= 16'h8000;
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ram_vshift <= 16'h8000;
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